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公开(公告)号：US08018711B2
公开(公告)日：2011-09-13
申请号：US12362986
申请日：2009-01-30
Applicant: Masaaki Togashi
Inventor： Masaaki Togashi
CPC classification number: H01G4/35 , H01G4/228 , H05K1/0231 , H05K2201/09772 , H05K2201/10636 , Y02P70/611
Abstract: A feedthrough capacitor has: a capacitor element body of a substantially rectangular parallelepiped shape in which a plurality of insulator layers are laminated together; a signal internal electrode arranged in the capacitor element body; a ground internal electrode arranged in the capacitor element body and opposed to the signal internal electrode; signal terminal electrodes connected to the signal internal electrode; and a ground terminal electrode connected to the ground internal electrode. The signal terminal electrodes are provided on first and second end faces, respectively, in a longitudinal direction of the capacitor element body. The ground terminal electrode is provided on at least one side face out of first to fourth side faces extending along the longitudinal direction of the capacitor element body. Furthermore, the ground terminal electrode is located nearer at least one end face out of the first end face and the second end face.
Abstract translation: 旁路电容器具有：大致长方体形状的电容器元件体，其中多个绝缘体层层叠在一起; 布置在所述电容器元件主体中的信号内部电极; 布置在电容器元件主体中并与信号内部电极相对的接地内部电极; 信号端子电极连接到信号内部电极; 以及连接到接地内部电极的接地端子电极。 信号端子电极分别设置在电容器元件主体的纵向上的第一和第二端面上。 接地端子电极设置在沿着电容器元件主体的纵向方向延伸的第一至第四侧面中的至少一个侧面上。 此外，接地端子电极位于比第一端面和第二端面更靠近的至少一个端面。
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公开(公告)号：US07982319B2
公开(公告)日：2011-07-19
申请号：US12637345
申请日：2009-12-14
Applicant: Yoshiharu Ogata
Inventor： Yoshiharu Ogata
IPC: H01L23/52
CPC classification number: H05K3/305 , H01L21/563 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/29007 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/83192 , H01L2225/06517 , H01L2225/06572 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K1/0271 , H05K3/3452 , H05K2201/09772 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2924/00014
Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.
Abstract translation: 半导体器件包括：布线基板，其包括布线图案; 安装在所述布线基板上的半导体芯片，包括与所述布线基板相对的形成在所述半导体芯片的表面上的多个焊盘; 覆盖所述布线图案的与所述半导体芯片重叠的区域的一部分上的第一树脂层; 以及安装在半导体芯片和第一树脂层之间的第二树脂层。 焊盘与暴露在第一树脂层上的布线图案的一部分相对并耦合; 并且布线基板的线膨胀系数大于半导体芯片的线膨胀系数，布线基板的弹性模量低于半导体芯片的弹性模量，并且第一树脂层的线膨胀系数大于第二树脂层的线膨胀系数 树脂层。 第一树脂层的弹性模量低于第二树脂层的弹性模量。
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143.发明申请WIRING BOARD, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权接线板，半导体器件及制造半导体器件的方法公开(公告)号：US20110042828A1
公开(公告)日：2011-02-24
申请号：US12988697
申请日：2009-03-16
Applicant: Yoshiki Sota , Kazuaki Tatsumi
Inventor： Yoshiki Sota , Kazuaki Tatsumi
CPC classification number: H01L23/49838 , H01L23/13 , H01L23/564 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45015 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H05K3/305 , H05K3/3452 , H05K2201/09072 , H05K2201/09772 , H05K2201/0989 , H05K2203/1178 , Y02P70/613 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/20752 , H01L2924/20753 , H01L2924/00015
Abstract: A wiring board (10) of the present invention includes: a through hole (11b), provided in a semiconductor chip mounted region (15), penetrating the wiring board (10); and a groove pattern (13), provided on a solder resist (9) formed on the semiconductor chip mounted region (15), leading to the through hole (11b). The foregoing configuration makes it possible to guide, via the groove pattern (13) to the through hole (11b), moisture that collects in the semiconductor chip mounted region (15) and therefore to effectively discharge the moisture from the semiconductor chip mounted region (15). Thus, a semiconductor device (30) that employs the wiring board (10) does not suffer from vaporization and expansion, inside of it, due to heat that is applied at the time of manufacturing the semiconductor device (30) and at the time of mounting the semiconductor device (30) on a mount substrate. It is therefore possible to reduce expansion of the semiconductor device.
Abstract translation: 本发明的布线基板（10）具备：贯通所述布线基板（10）的贯通孔（11b），设置在半导体芯片安装区域（15）中。 以及设置在形成在半导体芯片安装区域（15）上的阻焊剂（9）上的通向通孔（11b）的凹槽图案（13）。 上述构造使得可以经由凹槽图案（13）引导到通孔（11b），其收集在半导体芯片安装区域（15）中的湿气，并且因此有效地从半导体芯片安装区域排出水分（ 15）。 因此，采用该布线基板（10）的半导体装置（30）在制造半导体装置（30）时由于加热而在其内部不会发生汽化膨胀， 将半导体器件（30）安装在安装基板上。 因此可以减少半导体器件的膨胀。
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公开(公告)号：US07800462B2
公开(公告)日：2010-09-21
申请号：US12404999
申请日：2009-03-16
Applicant: Junichi Kurita , Kenji Kuranuki , Youichi Aoshima , Hiroshi Higashitani , Tsuyoshi Yoshino
Inventor： Junichi Kurita , Kenji Kuranuki , Youichi Aoshima , Hiroshi Higashitani , Tsuyoshi Yoshino
CPC classification number: H05K1/0231 , H01G9/012 , H01G9/28 , H05K1/165 , H05K2201/09772 , H05K2201/10015
Abstract: A printed board is mounted with a chip-type solid electrolytic capacitor of a four-terminal structure where a pair of positive electrode terminals are disposed at opposite positions and a pair of negative electrode terminals are disposed at opposite positions on a mounting surface. The printed board has a pair of positive electrode patterns and a pair of negative electrode patterns to which the positive electrode terminals and negative electrode terminals of the chip-type solid electrolytic capacitor are connected, respectively. The printed board further has an inductor section that is insulated from the negative electrode patterns, and electrically connects the positive electrode patterns.
Abstract translation: 印刷电路板安装有四端结构的芯片式固体电解电容器，其中一对正电极端子设置在相对位置，一对负电极端子设置在安装表面上的相对位置。 印刷电路板分别具有一对正电极图案和一对负电极图案，芯片型固体电解电容器的正极端子和负极端子分别连接到负极图案。 印刷电路板还具有与负电极图案绝缘的电感器部分，并且电连接正电极图案。
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145.发明申请公开(公告)号：US20100214697A1
公开(公告)日：2010-08-26
申请号：US12452488
申请日：2007-07-05
Applicant: Minggao Yao , Sun Yu , Lin Guo
Inventor： Minggao Yao , Sun Yu , Lin Guo
IPC: G11B5/48
CPC classification number: H05K1/111 , G11B5/4853 , H05K3/328 , H05K2201/09772 , H05K2201/10234 , H05K2201/10727 , Y02P70/611
Abstract: Aspects of the present invention include a system and method for improving the reliability performance of hard disk drives by routing the traces connected to the slider from the trailing edge to the leading edge and having a portion of the traces being under the magnetic slider. Aspects of the present invention can also include routing the traces in a manner that lessens the stress experienced during vibration or shock events.
Abstract translation: 本发明的方面包括一种用于通过将连接到滑块的迹线从后缘引导到前缘来改善硬盘驱动器的可靠性的系统和方法，并且具有一部分迹线在磁性滑动器之下。 本发明的方面还可以包括以减轻振动或冲击事件期间经受的应力的方式布置迹线。
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Patent Agency Ranking
公开(公告)号：US20100181101A1
公开(公告)日：2010-07-22
申请号：US12686533
申请日：2010-01-13
Applicant: Jang Soon HAN , Seung Myen Lee
Inventor： Jang Soon HAN , Seung Myen Lee
CPC classification number: H05K1/0216 , H05K1/0231 , H05K2201/093 , H05K2201/09336 , H05K2201/09772 , H05K2201/10522 , H05K2201/10545 , H05K2201/10689
Abstract: A printed circuit board (PCB) reduces a simultaneous switching noise (SSN) causing power noise, thereby reducing radiated electromagnetic interference (EMI). In a double-layered PCB, a first substrate is arranged in parallel with a second substrate while being spaced apart from the second substrate by a predetermined distance. The first substrate includes a ground plane, which is deposited over an entirety of the first substrate. The second substrate includes a power plane deposited at a position of a component mounted to the printed circuit board (PCB) to transmit power to the component. Thus, the power trace of the PCB is simplified in structure, thereby reducing EMI radiation noise.
Abstract translation: 印刷电路板（PCB）降低了产生电源噪声的同时开关噪声（SSN），从而降低了辐射电磁干扰（EMI）。 在双层PCB中，第一衬底与第二衬底平行地布置，同时与第二衬底隔开预定距离。 第一衬底包括沉积在整个第一衬底上的接地平面。 第二基板包括沉积在安装到印刷电路板（PCB）上的部件的位置以将功率传递到部件的电源平面。 因此，PCB的电源轨迹在结构上简化，从而降低EMI辐射噪声。
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公开(公告)号：US20090179335A1
公开(公告)日：2009-07-16
申请号：US12263614
申请日：2008-11-03
Applicant: Yun-Jin OH , Chang-Hoon HAN , Kwang-Ryul LEE , Hyoung-Suk KIM
Inventor： Yun-Jin OH , Chang-Hoon HAN , Kwang-Ryul LEE , Hyoung-Suk KIM
IPC: H01L23/485 , H05K1/18
CPC classification number: H05K3/3452 , H01L24/73 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06562 , H01L2924/15311 , H05K2201/09772 , H05K2201/09881 , H05K2203/0191 , H05K2203/049 , H05K2203/0577 , H05K2203/058 , H05K2203/0582 , H05K2203/0585 , H05K2203/1476 , Y10T29/4913 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
Abstract: A printed circuit board (PCB) and a semiconductor package that are configured to prevent delamination and voids. In one example embodiment, the semiconductor package includes a PCB having a base substrate on which conductive patterns are formed and which includes an interior region having a die paddle for receiving a semiconductor chip and an exterior region disposed outside the interior region. The PCB also includes a first solder resist formed on a portion of the base substrate corresponding to the interior region and a second solder resist formed on a portion of the base substrate corresponding to the exterior region. The second solder resist may also have a greater surface roughness than the surface roughness of the first solder resist.
Abstract translation: 配置为防止分层和空隙的印刷电路板（PCB）和半导体封装。 在一个示例性实施例中，半导体封装包括具有其上形成有导电图案的基底基板的PCB，其包括具有用于接收半导体芯片的管芯焊盘和设置在内部区域外部的外部区域的内部区域。 PCB还包括形成在对应于内部区域的基底基板的一部分上的第一阻焊剂和形成在对应于外部区域的基底基板的一部分上的第二阻焊剂。 第二阻焊剂也可以具有比第一阻焊剂的表面粗糙度更大的表面粗糙度。
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公开(公告)号：US07476975B2
公开(公告)日：2009-01-13
申请号：US11176782
申请日：2005-07-07
Applicant: Yoshiharu Ogata
Inventor： Yoshiharu Ogata
IPC: H01L23/52
CPC classification number: H05K3/305 , H01L21/563 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/29007 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/83192 , H01L2225/06517 , H01L2225/06572 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K1/0271 , H05K3/3452 , H05K2201/09772 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2924/00014
Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.
Abstract translation: 半导体器件包括：布线基板，其包括布线图案; 安装在所述布线基板上的半导体芯片，包括与所述布线基板相对的形成在所述半导体芯片的表面上的多个焊盘; 覆盖所述布线图案的与所述半导体芯片重叠的区域的一部分上的第一树脂层; 以及安装在半导体芯片和第一树脂层之间的第二树脂层。 焊盘与暴露在第一树脂层上的布线图案的一部分相对并耦合; 并且布线基板的线膨胀系数大于半导体芯片的线膨胀系数，布线基板的弹性模量低于半导体芯片的弹性模量，并且第一树脂层的线膨胀系数大于第二树脂层的线膨胀系数 树脂层。 第一树脂层的弹性模量低于第二树脂层的弹性模量。
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公开(公告)号：US20080277803A1
公开(公告)日：2008-11-13
申请号：US12174273
申请日：2008-07-16
Applicant: Yoshiharu OGATA
Inventor： Yoshiharu OGATA
IPC: H01L23/52
CPC classification number: H05K3/305 , H01L21/563 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/29007 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/83192 , H01L2225/06517 , H01L2225/06572 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K1/0271 , H05K3/3452 , H05K2201/09772 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2924/00014
Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.
Abstract translation: 半导体器件包括：布线基板，其包括布线图案; 安装在所述布线基板上的半导体芯片，包括与所述布线基板相对的形成在所述半导体芯片的表面上的多个焊盘; 覆盖所述布线图案的与所述半导体芯片重叠的区域的一部分上的第一树脂层; 以及安装在半导体芯片和第一树脂层之间的第二树脂层。 焊盘与暴露在第一树脂层上的布线图案的一部分相对并耦合; 并且布线基板的线膨胀系数大于半导体芯片的线膨胀系数，布线基板的弹性模量低于半导体芯片的弹性模量，并且第一树脂层的线膨胀系数大于第二树脂层的线膨胀系数 树脂层。 第一树脂层的弹性模量低于第二树脂层的弹性模量。
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150.发明授权公开(公告)号：US07449364B2
公开(公告)日：2008-11-11
申请号：US11460859
申请日：2006-07-28
Applicant: Kevin P. Lyne
Inventor： Kevin P. Lyne
CPC classification number: H01L23/49816 , H01L2924/0002 , H05K1/0231 , H05K1/113 , H05K3/3442 , H05K3/3452 , H05K3/4038 , H05K2201/0305 , H05K2201/0394 , H05K2201/09772 , H05K2201/10636 , Y02P70/611 , H01L2924/00
Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.
Abstract translation: 本发明提供一种用于将一个或多个无源部件构建成芯片级封装的方法和装置。 该方法包括以下步骤：选择具有芯片尺寸封装的封装球距的倍数的端子间距的无源元件，并将所选择的被动元件端子安装到封装的球位。 本发明的优选实施方案使用单一金属层聚酰胺胶带作为包装的基材。 公开了本发明的另外的优选实施例，其中包装球间距的端子间距倍数是一个或两个。 还公开了对应于所公开的方法的设备。
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