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公开(公告)号：US20160327242A1
公开(公告)日：2016-11-10
申请号：US14799383
申请日：2015-07-14
Applicant: LUSTROUS TECHNOLOGY LTD.
Inventor： Kao-Hsu CHOU , Juei-Khai LIU , Chia-Chi LIU
CPC classification number: F21V7/04 , F21K9/00 , F21V17/06 , F21V23/005 , F21V23/006 , F21V29/89 , F21Y2115/10 , H05K1/113 , H05K1/184 , H05K2201/0979 , H05K2201/10106 , H05K2203/167
Abstract: A compact LED module includes: a circuit substrate, formed with an opening, a pair of combination holes and at least one through via area formed with a plurality of through vias; a reflection cup, formed with a light inlet, a light outlet and a pair of combination posts, wherein the pair of combination posts are combined with the pair of combination holes for allowing the reflection cup to be fastened on a first surface of the circuit substrate, and the light inlet is aligned with the opening; and a LED unit, installed with a LED light source and formed with at least one soldering area, wherein each of the soldering areas is connected to each of the through via areas by utilizing solder, thereby allowing the LED unit to be fastened on a second surface of the circuit substrate, and the LED light source is aligned with the opening.
Abstract translation: 紧凑型LED模块包括：形成有开口的电路基板，一对组合孔和形成有多个通孔的至少一个通孔区域; 形成有光入口，光出口和一对组合柱的反射杯，其中所述一对组合柱与所述一对组合孔组合以允许将所述反射杯紧固在所述电路基板的第一表面上 并且光入口与开口对准; 以及LED单元，其安装有LED光源并且形成有至少一个焊接区域，其中每个焊接区域通过利用焊料连接到每个通孔区域，从而允许将LED单元紧固在第二 电路基板的表面，并且LED光源与开口对准。
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142.发明授权Suspension board assembly sheet with circuits and method for manufacturing the same 有权具有电路的悬挂板组装片及其制造方法公开(公告)号：US09451704B2
公开(公告)日：2016-09-20
申请号：US14062264
申请日：2013-10-24
Applicant: Nitto Denko Corporation
Inventor： Terukazu Ihara , Jun Ishii , Naohiro Terada
CPC classification number: H05K3/10 , G11B5/486 , H05K1/0228 , H05K1/0245 , H05K1/025 , H05K1/0265 , H05K1/056 , H05K3/0097 , H05K3/06 , H05K3/4685 , H05K2201/09236 , H05K2201/09254 , H05K2201/09509 , H05K2201/09554 , H05K2201/09627 , H05K2201/0979 , H05K2203/0323 , Y10T29/49155
Abstract: A plurality of suspension boards and an inspection substrate are integrally supported by a support frame. In each suspension board, a line is formed on a conductive first support substrate via a first insulating layer. The first support substrate and the line are electrically connected by a first via in the first insulating layer. In the inspection substrate, a conductor layer is formed on a conductive second support substrate with a second insulating layer sandwiched therebetween. The second support substrate and the conductor layer are electrically connected by a second via in the second insulating layer. The first via and the second via have the same configuration.
Abstract translation: 多个悬挂板和检查基板由支撑框架一体地支撑。 在每个悬挂板中，经由第一绝缘层在导电的第一支撑基板上形成线。 第一支撑基板和线通过第一绝缘层中的第一通孔电连接。 在检查基板中，导电层形成在导电性的第二支撑基板上，其间夹着第二绝缘层。 第二支撑基板和导体层通过第二绝缘层中的第二通孔电连接。 第一通孔和第二通孔具有相同的配置。
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公开(公告)号：US09406532B2
公开(公告)日：2016-08-02
申请号：US14221486
申请日：2014-03-21
Applicant: Tessera, Inc.
Inventor： Belgacem Haba , Ilyas Mohammed
IPC: H01L21/44 , H01L21/48 , H01L23/498 , H05K3/40
CPC classification number: H01L21/486 , H01L23/49827 , H01L23/49861 , H01L23/49894 , H01L2224/16225 , H01L2924/09701 , H01L2924/15311 , H05K3/4046 , H05K2201/0979 , H05K2201/10378 , H05K2201/10674
Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.
Abstract translation: 公开了一种用于制造互连部件的方法，包括形成远离参考表面延伸的多个金属柱。 每个柱形成具有一对相对的端面和在它们之间延伸的边缘表面。 形成接触边缘表面和相邻柱之间的填充空间的电介质层。 电介质层具有邻近第一和第二端面的第一和第二相对表面。 电介质层的热膨胀系数小于8ppm /℃。互连部件完成，使得它们在横向方向上延伸的柱的第一和第二端面之间没有互连。 第一和第二多个可湿接触部分邻近第一和第二相对表面。 可湿接触可用于将互连部件连接到微电子元件或电路板。
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公开(公告)号：US20160192489A1
公开(公告)日：2016-06-30
申请号：US14962634
申请日：2015-12-08
Applicant: FUJITSU LIMITED
Inventor： Yuki KANAI , Takashi IMAMOTO
CPC classification number: H05K1/144 , G06F1/189 , G06F1/26 , H05K1/0265 , H05K1/113 , H05K1/141 , H05K2201/042 , H05K2201/09309 , H05K2201/0979 , H05K2201/10242 , H05K2201/10303
Abstract: A power supply board includes: a first board including a top surface on which a processor is capable of being mounted, a bottom surface located on an opposite side of the top surface, and a plurality of first through holes and a plurality of second through holes capable of being electrically connected with the processor by penetrating through the first board from the top surface to the bottom surface; a second board arranged at a position distant from the bottom surface of the first board and provided with a power supply device; a first conductor mounted on the bottom surface of the first board and electrically connects the plurality of first through holes and the power supply device, and a second conductor mounted on the bottom surface of the first board and electrically connects the plurality of second through holes and the power supply device.
Abstract translation: 电源板包括：第一板，其包括可在其上安装处理器的顶表面，位于顶表面相对侧的底表面，以及多个第一通孔和多个第二通孔 能够通过从顶表面穿透第一板到底表面而与处理器电连接; 布置在远离所述第一板的底表面的位置并且设置有电源装置的第二板; 第一导体，其安装在所述第一板的底表面上，并且电连接所述多个第一通孔和所述电源装置;以及第二导体，其安装在所述第一板的底表面上，并且电连接所述多个第二通孔和 电源装置。
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公开(公告)号：US09277642B2
公开(公告)日：2016-03-01
申请号：US14012216
申请日：2013-08-28
Applicant: Eastman Kodak Company
Inventor： Ronald Steven Cok
CPC classification number: H05K1/0274 , H05K1/0298 , H05K1/097 , H05K3/0041 , H05K3/12 , H05K3/1258 , H05K3/1275 , H05K3/1283 , H05K3/1291 , H05K3/465 , H05K3/4685 , H05K2201/09209 , H05K2201/09281 , H05K2201/0979 , H05K2201/09845 , H05K2203/0108
Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing first, second, and third different stamps. A curable bottom, connecting layer, and top layer are formed on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer in the central area and the edge area, a connecting-layer micro-channel is imprinted in the connecting layer in the edge area over the bottom-layer micro-channel, an edge micro-channel is imprinted in the top layer in the edge area over the connecting-layer micro-channel, and top-layer micro-channels are imprinted in the top layer over the central area. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire.
Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一，第二和第三不同的邮票。 在基板上形成可固化的底部，连接层和顶层。 底层微通道印在中心区域和边缘区域的底层中，连接层微通道被压印在底层微通道上的边缘区域中的连接层中，边缘 微通道印在连接层微通道上的边缘区域的顶层中，顶层微通道印在中心区域的顶层中。 微线形成在每个微通道中。 中心区域的底层微线电连接到边缘区域中的边缘微线，并与顶层微线电隔离。
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Patent Agency Ranking
公开(公告)号：US09243791B2
公开(公告)日：2016-01-26
申请号：US14243521
申请日：2014-04-02
Applicant: Sharp Kabushiki Kaisha
Inventor： Makoto Agatani , Toshio Hata , Tomokazu Nada , Shinya Ishizaki
CPC classification number: H01L25/0753 , F21K9/00 , F21K9/232 , F21V23/06 , F21Y2101/00 , F21Y2105/10 , F21Y2115/10 , H01L33/483 , H01L33/52 , H01L33/54 , H01L33/62 , H01L2224/48091 , H01L2224/48137 , H01L2924/01327 , H01L2933/0066 , H05K1/11 , H05K2201/0391 , H05K2201/094 , H05K2201/0979 , H05K2201/10106 , H01L2924/00014 , H01L2924/00
Abstract: A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical use, by both connecting methods with a solder and a connector, and a lighting device provided with the light-emitting device are provided. The light-emitting device according to the present invention has a plurality of LED chips, and a soldering electrode land and a connector connecting electrode land electrically connected to the chips, on a ceramic substrate. The soldering electrode land is formed of a first conductive material having a function to prevent diffusion to a solder, and the connector connecting electrode land is formed of a second conductive material having a function to prevent oxidation.
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公开(公告)号：US09215798B2
公开(公告)日：2015-12-15
申请号：US14012173
申请日：2013-08-28
Applicant: Ronald Steven Cok
Inventor： Ronald Steven Cok
CPC classification number: H05K1/0274 , H05K1/0298 , H05K1/097 , H05K3/0041 , H05K3/12 , H05K3/1258 , H05K3/1275 , H05K3/1283 , H05K3/1291 , H05K3/465 , H05K3/4685 , H05K2201/09209 , H05K2201/09281 , H05K2201/0979 , H05K2201/09845 , H05K2203/0108
Abstract: A method of making an imprinted micro-wire structure includes providing a substrate, a first stamp, and a different multi-level second stamp. A curable bottom layer is provided over the substrate. One or more bottom-layer micro-channel(s) are imprinted in the curable bottom layer with the first stamp and a bottom-layer micro-wire formed in each bottom-layer micro-channel. A curable multi-layer is formed adjacent to and in contact with the cured bottom layer. First and second multi-layer micro-channels and a top-layer micro-channel are imprinted in the curable multi-layer with the multi-level second stamp. Either two bottom-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a top-layer micro-wire or two top-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a bottom-layer micro-wire.
Abstract translation: 制造压印微线结构的方法包括提供衬底，第一印模和不同的多级第二印模。 在基板上设置可固化的底层。 一个或多个底层微通道被印刷在可固化底层中，第一印模和底层微线形成在每个底层微通道中。 在固化的底层附近形成可固化的多层，并且与固化的底层接触。 第一和第二多层微通道和顶层微通道用多级第二印记印在可固化多层中。 两个底层微电线通过第一和第二多层微线电连接，并且顶层微线或两个顶层微线通过第一和第二多层微电子电连接 电线和底层微线。
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公开(公告)号：US09188321B2
公开(公告)日：2015-11-17
申请号：US14521105
申请日：2014-10-22
Applicant: Sharp Kabushiki Kaisha
Inventor： Makoto Agatani , Toshio Hata , Tomokazu Nada , Shinya Ishizaki
CPC classification number: H01L25/0753 , F21K9/00 , F21K9/232 , F21V23/06 , F21Y2101/00 , F21Y2105/10 , F21Y2115/10 , H01L33/483 , H01L33/52 , H01L33/54 , H01L33/62 , H01L2224/48091 , H01L2224/48137 , H01L2924/01327 , H01L2933/0066 , H05K1/11 , H05K2201/0391 , H05K2201/094 , H05K2201/0979 , H05K2201/10106 , H01L2924/00014 , H01L2924/00
Abstract: A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical use, by both connecting methods with a solder and a connector, and a lighting device provided with the light-emitting device are provided. The light-emitting device according to the present invention has a plurality of LED chips, and a soldering electrode land and a connector connecting electrode land electrically connected to the chips, on a ceramic substrate. The soldering electrode land is formed of a first conductive material having a function to prevent diffusion to a solder, and the connector connecting electrode land is formed of a second conductive material having a function to prevent oxidation.
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公开(公告)号：US20150282297A1
公开(公告)日：2015-10-01
申请号：US14730720
申请日：2015-06-04
Applicant: Tyco Electronics AMP Korea Ltd.
Inventor： Yang Yun Choi , Ok Ky Beak
CPC classification number: H05K1/0213 , H05K1/092 , H05K1/116 , H05K1/182 , H05K3/244 , H05K3/325 , H05K3/423 , H05K3/429 , H05K3/445 , H05K3/4608 , H05K2201/0979 , H05K2201/1059 , H05K2201/1081 , H05K2203/0723 , H05K2203/073
Abstract: A printed circuit board has a substrate having a circuit pattern; a primary component receiving hole positioned on the substrate and having an inner surface electrically connected with the circuit pattern; and at least one secondary component receiving hole positioned on the substrate around the primary component receiving hole, and having an inner surface electrically connected with the circuit pattern and the inner surface of the primary component receiving hole.
Abstract translation: 印刷电路板具有具有电路图案的基板; 主要部件接收孔，其位于所述基板上并且具有与所述电路图案电连接的内表面; 以及至少一个辅助部件容纳孔，位于基体周围的主要部件容纳孔上，并且具有与电路图案和主要部件容纳孔的内表面电连接的内表面。
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公开(公告)号：US09101056B2
公开(公告)日：2015-08-04
申请号：US14012240
申请日：2013-08-28
Applicant: Eastman Kodak Company
Inventor： Ronald Steven Cok
CPC classification number: H05K1/0274 , H05K1/0298 , H05K1/097 , H05K3/0041 , H05K3/12 , H05K3/1258 , H05K3/1275 , H05K3/1283 , H05K3/1291 , H05K3/465 , H05K3/4685 , H05K2201/09209 , H05K2201/09281 , H05K2201/0979 , H05K2201/09845 , H05K2203/0108
Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing a first stamp and a multi-level second stamp. A curable bottom layer and multi-layer are provided on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer. A multi-layer micro-channel and a top-layer micro-channel are imprinted in the multi-layer. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire extends from the central area into the edge area. The multi-layer micro-wire contacts the bottom-layer micro-wire in the edge area. The top-layer micro-wire is over the central area and is separate from the multi-layer micro-wire and the bottom-layer micro-channel. The bottom-layer micro-wire is electrically connected to the multi-layer micro-wire and is electrically isolated from the top-layer micro-wire.
Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一印模和多级第二印模。 在基板上设置有可固化的底层和多层。 底层微通道印在底层中。 多层微通道和顶层微通道印在多层中。 微线形成在每个微通道中。 底层微线从中心区域延伸到边缘区域。 多层微线接触边缘区域的底层微线。 顶层微线在中心区域之上，与多层微线和底层微通道分离。 底层微线电连接到多层微线，并与顶层微线电隔离。
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