公开(公告)号：US20080298038A1

公开(公告)日：2008-12-04

申请号：US12126329

申请日：2008-05-23

Applicant: Kentaro Kaneko

Inventor： Kentaro Kaneko

IPC: H05K7/02 ,  H01R43/00

CPC classification number: H05K3/007 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/181 ,  H05K1/113 ,  H05K3/06 ,  H05K3/205 ,  H05K3/243 ,  H05K3/4038 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2203/0376 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49224 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring board has predetermined numbers of wiring layers and insulating layers among the respective wiring layers. The wiring board has an external connecting pad and a surface plating layer for connecting to an external circuit is arranged on the external connecting pad. An area of an external connecting pad is smaller than an area of a surface plating layer thereof.

Abstract translation: 布线板在各布线层之间具有预定数量的布线层和绝缘层。 布线板具有外部连接焊盘，并且用于连接到外部电路的表面镀层布置在外部连接焊盘上。 外部连接焊盘的面积小于其表面镀层的面积。

公开(公告)号：US20080251289A1

公开(公告)日：2008-10-16

申请号：US12136308

申请日：2008-06-10

Applicant: JOSEPH P. PALMERI ,  Vincent P. Mulligan

Inventor： JOSEPH P. PALMERI ,  Vincent P. Mulligan

IPC: H01R12/04

CPC classification number: H05K3/225 ,  H05K1/113 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/4046 ,  H05K2201/09845 ,  H05K2201/10303 ,  H05K2203/0191 ,  H05K2203/0242 ,  Y10T29/49174 ,  Y10T29/49179

Abstract: Methods and devices are provided for repairing a damaged contact pad that is located on a first surface of a printed circuit board and connected to a via that passes through the circuit board. According to the method, a countersink hole is created in the first surface of the printed circuit board in a location that is substantially centered on an axis passing through the via, and a replacement structure is inserted into the countersink hole. The replacement structure has a stem portion, a head portion, and a shoulder portion that connects the stem and head portions, with the angle of the shoulder portion substantially matching the angle of the shoulder of the countersink hole. The stem portion of the replacement structure is permanently attached to sidewalls of the via so as to electrically couple the head portion of the replacement structure to the via.

Abstract translation: 提供了用于修复位于印刷电路板的第一表面上并连接到通过电路板的通孔的损坏的接触垫的方法和装置。 根据该方法，在印刷电路板的第一表面中形成基本上位于通过通孔的轴的中心的位置上形成埋头孔，并且将更换结构插入到埋头孔中。 替换结构具有杆部，头部和肩部，其连接杆和头部，肩部的角度基本上与埋头孔的肩部的角度相匹配。 替换结构的杆部分永久地附接到通孔的侧壁，以便将替换结构的头部部分电连接到通孔。

公开(公告)号：US07418780B2

公开(公告)日：2008-09-02

申请号：US11560787

申请日：2006-11-16

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: H01K3/10 ,  H05K3/36

CPC classification number: H05K3/4652 ,  H05K3/0035 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An exemplary method for forming stacked via-holes in a multilayer printed circuit board includes the steps of: providing a base circuit board; attaching a first copper-coated-substrate having a first substrate and a first copper layer thereon and a second copper-coated-substrate having a second substrate and a second copper layer thereon onto the base circuit board in a manner such that; forming at least one first window in the second copper layer, making at least one first hole in the second substrate through the at least one first window, forming at least one second window in the first copper layer through the at least one first hole, and making at least one second hole in the first substrate through the at least one second window, thus forming at least one part-finished stacked via-hole; and plating the at least one part-finished stacked via-hole thereby forming at least one stacked via-hole.

Abstract translation: 在多层印刷电路板中形成堆叠的通孔的示例性方法包括以下步骤：提供基底电路板; 将其上具有第一基板和第一铜层的第一铜涂覆基板和其上具有第二基板和第二铜层的第二铜涂覆基板以如下方式附接到基板电路板上; 在所述第二铜层中形成至少一个第一窗口，通过所述至少一个第一窗口在所述第二基板中形成至少一个第一孔，通过所述至少一个第一孔在所述第一铜层中形成至少一个第二窗口，以及 通过所述至少一个第二窗口在所述第一基板中形成至少一个第二孔，从而形成至少一个部分完成的堆叠通孔; 以及对所述至少一个部分精加工的堆叠通孔进行电镀，从而形成至少一个堆叠的通孔。

公开(公告)号：US20080176035A1

公开(公告)日：2008-07-24

申请号：US12016593

申请日：2008-01-18

Applicant: Chao-Wen Shih ,  Zhao-Chong Zeng

Inventor： Chao-Wen Shih ,  Zhao-Chong Zeng

IPC: H05K1/02 ,  B32B3/10 ,  H05K3/00

CPC classification number: H05K3/243 ,  H01L2224/05018 ,  H05K3/0023 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09845 ,  H05K2203/054 ,  H05K2203/0577 ,  Y10T428/24273

Abstract: A circuit board structure and a fabrication method of the same are disclosed according to the present invention. The circuit board structure includes: a carrier board with at least one surface formed with a circuit layer having electrically connecting pads; a first solder mask formed on the carrier board and the circuit layer and formed with first openings for exposing the electrically connecting pads; and a second solder mask formed on the first solder mask and formed with second openings for exposing the first openings and the electrically connecting pads. The first solder mask is made of a high-insulation photosensitive material characterized by presence or absence of impurities, such as microparticles, to have enhanced fluidity for being filled in the circuit layer, thereby preventing metal ions migration and subsequent metal hypha electricity discharge which might otherwise affect electrical performance, therefore the present invention is applicable to fine circuit fabrication.

Abstract translation: 根据本发明公开了一种电路板结构及其制造方法。 电路板结构包括：承载板，其至少一个表面形成有具有电连接焊盘的电路层; 形成在所述载体板和所述电路层上并形成有用于暴露所述电连接焊盘的第一开口的第一焊料掩模; 以及形成在第一焊料掩模上并形成有用于暴露第一开口和电连接焊盘的第二开口的第二焊料掩模。 第一焊料掩模由高绝缘感光材料制成，其特征在于存在或不存在诸如微粒之类的杂质，以提高填充在电路层中的流动性，从而防止金属离子迁移和随后的金属菌丝放电，这可能 否则会影响电气性能，因此本发明适用于精细电路制造。

公开(公告)号：US20080168651A1

公开(公告)日：2008-07-17

申请号：US11652633

申请日：2007-01-12

Applicant: Ashwinkumar C. Bhatt ,  Robert J. Harendza ,  Robert M. Japp

Inventor： Ashwinkumar C. Bhatt ,  Robert J. Harendza ,  Robert M. Japp

IPC: H05K3/36

CPC classification number: H05K1/117 ,  H05K1/112 ,  H05K3/4611 ,  H05K2201/09127 ,  H05K2201/0919 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2203/061 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: A method of making a printed circuit board in which at least three substrates are aligned and bonded together (e.g., using lamination). Two of the substrates have openings formed therein, with each opening including a cover member located therein. During lamination, the cover members for a seal and prevent dielectric material (e.g., resin) liquefied during the lamination from contacting the conductive layers on the opposed surfaces of the inner (first) substrate. A PCB is thus formed with either a projecting edge portion or a plurality of cavities therein such that electrical connection may be made to the PCB using an edge connector or the like.

Abstract translation: 制造印刷电路板的方法，其中至少三个基板被对准并结合在一起（例如，使用层压）。 两个基板具有形成在其中的开口，每个开口包括位于其中的盖构件。 在层压期间，用于密封和防止介电材料（例如树脂）的盖构件在层压期间液化以接触内（第一）衬底的相对表面上的导电层。 因此，PCB在其中形成有突出边缘部分或多个空腔，使得可以使用边缘连接器等对PCB进行电连接。

公开(公告)号：US20080070000A1

公开(公告)日：2008-03-20

申请号：US11888543

申请日：2007-07-31

Applicant: Jin Suzuki

Inventor： Jin Suzuki

IPC: B32B3/10 ,  H01R43/00

CPC classification number: H05K1/183 ,  H01L23/057 ,  H01L23/13 ,  H01L23/5385 ,  H01L25/165 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  H01L2924/19106 ,  H01R12/523 ,  H05K1/182 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09845 ,  H05K2201/10477 ,  H05K2201/10727 ,  Y10T29/49004 ,  Y10T29/49124 ,  Y10T428/24331 ,  H01L2224/0401

Abstract: A circuit module includes a multilayer wiring board having a cavity portion and an interposer on which a chip part is mounted. The interposer is bonded to the multilayer wiring board so that the chip part is disposed in the cavity portion and the cavity portion is hermetically sealed. In the manufacturing process for the circuit module, a continuity test of the chip part is conducted by applying a testing voltage to the interposer before the interposer is bonded to the multilayer wiring board.

Abstract translation: 电路模块包括具有空腔部分和插入件的多层布线板，其上安装有芯片部分。 插入器与多层布线板接合，使得芯片部分设置在空腔部分中并且空腔部分被气密密封。 在电路模块的制造工序中，通过在插入件与多层布线板接合之前，向插入件施加测试电压来进行芯片部分的连续性测试。

公开(公告)号：US20080012117A1

公开(公告)日：2008-01-17

申请号：US11752770

申请日：2007-05-23

Applicant: Shin KIM

Inventor： Shin KIM

IPC: H01L23/48 ,  H01L21/30 ,  H01L21/58

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L23/13 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/12 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/105 ,  H01L2224/03334 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/16105 ,  H01L2224/16157 ,  H01L2224/274 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2225/1005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H05K1/183 ,  H05K1/184 ,  H05K2201/09845 ,  H05K2201/10477 ,  H05K2201/10727 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided are a semiconductor package having connection terminals whose side surfaces are exposed and a semiconductor module including such a semiconductor package. Also provided are methods of fabricating the semiconductor package and semiconductor module. According to an embodiment of the present invention, a semiconductor package includes a semiconductor chip including a semiconductor wafer having first and second opposite surfaces and a plurality of conductive pads arranged in a row on the first surface along the edges of the semiconductor wafer such that a side surface of each conductive pad is exposed. An insulating layer is formed on the first surface of the semiconductor wafer and includes openings for exposing parts of the conductive pads. A plurality of connection terminals are respectively arranged on the conductive pads exposed through the openings and a reinforcing member is arranged on the insulating layer to cover a portion of each connection terminal.

Abstract translation: 提供了具有侧表面露出的连接端子和包括这种半导体封装的半导体模块的半导体封装。 还提供了制造半导体封装和半导体模块的方法。 根据本发明的实施例，半导体封装包括半导体芯片，其包括具有第一和第二相对表面的半导体晶片和沿着半导体晶片的边缘在第一表面上排成一行的多个导电焊盘，使得 每个导电焊盘的侧面露出。 绝缘层形成在半导体晶片的第一表面上，并且包括用于暴露导电焊盘部分的开口。 多个连接端子分别布置在通过开口暴露的导电焊盘上，并且在绝缘层上布置加强构件以覆盖每个连接端子的一部分。

公开(公告)号：US20070281505A1

公开(公告)日：2007-12-06

申请号：US11547690

申请日：2005-04-04

Applicant: Atsushi Kobayashi ,  Kazuo Umeda ,  Wataru Gotou ,  Susumu Nakazawa ,  Kiyoshi Takeuchi ,  Takayuki Terauchi

Inventor： Atsushi Kobayashi ,  Kazuo Umeda ,  Wataru Gotou ,  Susumu Nakazawa ,  Kiyoshi Takeuchi ,  Takayuki Terauchi

IPC: H05K3/46 ,  H05K1/02 ,  H05K1/14 ,  H05K3/36

CPC classification number: H05K3/4691 ,  H05K3/0052 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/0187 ,  H05K2201/0919 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0169 ,  H05K2203/061

Abstract: A rigid-flexible board and a method for manufacturing the same can be provided, whereby the material yield ratio can be enhanced and the productive yield can be also enhanced. A rigid board with a step for connection and a flexible board with a connector at the edge thereof are formed independently. Then, the connecting area is spot facing processed so that the depth of the thus obtained depressed portion is equal to or lower than the thickness of the flexible board. The connector of the flexible board is electrically connected to the vertical wiring area of the depressed portion.

Abstract translation: 可以提供刚性柔性板及其制造方法，从而可以提高材料屈服比，并且还可以提高生产率。 独立地形成具有用于连接的台阶的刚性板和在其边缘处具有连接器的柔性板。 然后，连接区域被加工成正面，使得如此获得的凹陷部分的深度等于或低于柔性板的厚度。 柔性板的连接器电连接到凹陷部分的垂直布线区域。

公开(公告)号：US07265299B2

公开(公告)日：2007-09-04

申请号：US10794008

申请日：2004-03-04

Applicant: Shuo Hsiu Hu ,  Chih-Feng Sung

Inventor： Shuo Hsiu Hu ,  Chih-Feng Sung

IPC: H05K1/09

CPC classification number: H05K1/0265 ,  H05K2201/098 ,  H05K2201/09845 ,  H05K2201/09909

Abstract: A conducting device for a display device is disclosed. It comprises one or more non-conducting base lines formed in predetermined locations on a substrate layer, and one or more conducting line structures formed over the non-conducting base lines on the substrate layer, wherein the non-conducting base lines raise the conducting line structures in height for increasing a cross-sectional area thereof for reducing a resistance of the conducting line structures.

Abstract translation: 公开了一种用于显示装置的导电装置。 它包括一个或多个形成在基底层上的预定位置的非导电基线，以及一个或多个导电线结构，形成在基底层上的非导电基线之上，其中非导电基线增加导线 用于增加其横截面面积以降低导线结构的电阻的高度结构。

公开(公告)号：US07219242B2

公开(公告)日：2007-05-15

申请号：US10404185

申请日：2003-03-31

Applicant: Martin D. Goodman

Inventor： Martin D. Goodman

IPC: G06F1/26

CPC classification number: H05K1/117 ,  H01R12/7088 ,  H01R13/26 ,  H01R24/44 ,  H05K2201/0919 ,  H05K2201/09845

Abstract: According to one embodiment of the present invention, a method for low impedance power delivery is disclosed. The method includes: providing a module, the module having a plurality of layers including a top layer; removing the top layer of the module to expose a power delivery plane; and providing a plurality of signal contacts on the top layer of the module to communicate signals between the module and an external device.

Abstract translation: 根据本发明的一个实施例，公开了一种用于低阻抗功率输送的方法。 该方法包括：提供模块，该模块具有包括顶层的多个层; 去除模块的顶层以暴露电力输送平面; 以及在模块的顶层上提供多个信号触点，以在模块和外部设备之间传送信号。