公开(公告)号：US06550117B1

公开(公告)日：2003-04-22

申请号：US09595912

申请日：2000-06-20

Applicant: Yasumichi Tokuoka ,  Takeshi Nomura

Inventor： Yasumichi Tokuoka ,  Takeshi Nomura

IPC: H01G700

CPC classification number: H05K3/4667 ,  H01G4/30 ,  H01G4/308 ,  H05K1/0306 ,  H05K3/046 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/0528 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49128

Abstract: Internal electrode layers of a multilayer ceramic electronic element are structured such that spaces, which are formed between adjacent internal electrodes, are eliminated so as to substantially flatten the internal electrode layers. Moreover, the thickness of each green dielectric layer is reduced. To achieve this, a laminating process is performed by a thermal transfer printing method such that a thermal transfer conductor material and a thermal transfer dielectric material are used so as to form internal electrode portions and green dielectric portions. Thus, the internal electrode layers are formed.

Abstract translation: 多层陶瓷电子元件的内部电极层被构造为使得在相邻的内部电极之间形成的空间被消除，以使内部电极层基本上平坦化。 此外，每个绿色介电层的厚度减小。 为了实现这一点，通过使用热转印导体材料和热转印介电材料以形成内部电极部分和绿色电介质部分的热转印印刷方法进行层压工艺。 因此，形成内部电极层。

公开(公告)号：US20030066680A1

公开(公告)日：2003-04-10

申请号：US10256542

申请日：2002-09-26

Applicant: Alps Electric Co., Ltd.

Inventor： Katsuya Kikuiri ,  Takashi Takabatake

IPC: H05K001/09

CPC classification number: G11B5/3967 ,  G11B5/3103 ,  G11B5/3109 ,  G11B5/48 ,  G11B5/53 ,  H05K1/112 ,  H05K3/243 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09436 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0733

Abstract: A terminal electrode provided on a lead joint of a thin-film device fabricated by a thin-film technology. The terminal electrode is constituted by an upper pad and a lower pad, the lower pad being formed into a pillar-like shape protuberantly projecting from the lead joint. The upper pad, which is wider than the lower pad, is formed on the lower pad such that the center thereof is aligned with the center of the lower pad. This arrangement provides the terminal electrode that allows a higher-density insulating layer free of defects, such as voids, to be formed around the terminal electrode, leading to an improved mounting strength of the terminal electrode.

Abstract translation: 设置在通过薄膜技术制造的薄膜器件的引线接头上的端子电极。 端子电极由上焊盘和下焊盘构成，下焊盘形成为从引线接头突出地突出的柱状形状。 比下垫宽的上衬垫形成在下垫上，使得其中心与下垫的中心对准。 这种布置提供了允许在端子电极周围形成无空隙缺陷的更高密度绝缘层的端子电极，导致端电极的安装强度提高。

公开(公告)号：US06512186B1

公开(公告)日：2003-01-28

申请号：US09719548

申请日：2000-12-22

Applicant: Yoko Nishiwaki ,  Kouta Noda

Inventor： Yoko Nishiwaki ,  Kouta Noda

IPC: H01R1204

CPC classification number: H05K3/4626 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/0094 ,  H05K3/384 ,  H05K3/385 ,  H05K3/4602 ,  H05K2201/0108 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0278 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/1157 ,  Y10T29/49155

Abstract: A multilayer printed wiring board has such a structure that conductor circuit patterns are formed on a core substrate through interlaminar resin insulating layers and through-holes are formed in the core substrate and a filler is filled in the through-hole. The interlaminar resin insulating layer formed on the substrate is flat and the same kind of roughened layer is formed on the conductor circuit pattern on the substrate over a full surface including a side surface thereof. A cover plated layer is formed just above the through-hole, and the roughened layers are formed on the conductor layer and the conductor circuit pattern located at the same level as the conductor layer over a full surface including side surfaces thereof, and the interlaminar resin insulating layer is formed so as to cover the surfaces of these roughened layers and filled in recess portions between the conductors and flattened on its surface. Thus, it is excellent in the crack resistance under heat cycle condition or the like and does not cause the damage of the cover plated layer.

Abstract translation: 多层印刷布线板具有通过层间树脂绝缘层在芯基板上形成导体电路图案的结构，并且在芯基板中形成通孔，并且在通孔中填充填料。 形成在基板上的层间树脂绝缘层是平坦的，并且在包括其侧表面的整个表面上的基板上的导体电路图案上形成相同种类的粗糙层。 在通孔的正上方形成覆盖层，并且在导体层和导体电路图案上形成粗糙层，该导体层和导体电路图案位于与导体层相同的整个表面的整个表面上，包括其侧表面，并且层间树脂 形成绝缘层以覆盖这些粗糙层的表面并填充在导体之间的凹部中并在其表面上变平。 因此，在热循环条件等下的耐龟裂性优异，不会引起覆盖层的损伤。

公开(公告)号：US06499214B2

公开(公告)日：2002-12-31

申请号：US09812449

申请日：2001-03-20

Applicant: Delin Li ,  Richard Keith McMillan ,  Zhong-You Shi

Inventor： Delin Li ,  Richard Keith McMillan ,  Zhong-You Shi

IPC: H05K320

CPC classification number: H05K3/429 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method 10, 110 for making multi-layer circuit boards having metallized apertures 38, 40, 130, 132 which may be selectively and electrically grounded and having at least one formed air-bridge 92, 178.

Abstract translation: 一种用于制造具有金属化孔38,40,130,132的多层电路板的方法10,110，其可以选择性地和电接地并且具有至少一个形成的空气桥92,178。

公开(公告)号：US20020181211A1

公开(公告)日：2002-12-05

申请号：US10088035

申请日：2002-06-28

Inventor： Masaki Suzumura ,  Fumiaki Hashimoto

IPC: H05K005/00 ,  H05K005/04 ,  H05K005/06

CPC classification number: H05K1/056 ,  H01L2924/0002 ,  H05K1/0373 ,  H05K3/202 ,  H05K3/28 ,  H05K2201/0209 ,  H05K2201/09881 ,  Y10S428/901 ,  Y10T428/12514 ,  Y10T428/12556 ,  Y10T428/24917 ,  Y10T428/31681 ,  H01L2924/00

Abstract: A circuit board of the present invention comprises a composite resin and a metal plate, and the metal plate forms circuit patterns. The metal plate is preferably made of copper or copper alloys having excellent heat conductivity. The composite resin comprises 70-95 parts by weight of inorganic filler, and 5-30 parts by weight of a resin composition including a thermosetting resin and a hardener. The metal plate is surface roughened or treated to reinforce the adhesion at least at one surface contacting with the composite resin. In the circuit board of the present invention, the composite resin fills spaces between the circuit patterns, and the composite resin composition and the metal plate form a plane at the side of the metal plate for mounting components. In the circuit board of the present invention, since the resin composition including the inorganic filler is also present in the spaces between circuit patterns of a metal plate, its heat dissipation characteristic is extremely high, and it is suited as a circuit board for electronic apparatus containing heat generating parts such as power circuit.

Abstract translation: 本发明的电路板包括复合树脂和金属板，并且金属板形成电路图案。 金属板优选由具有优异导热性的铜或铜合金制成。 复合树脂包含70-95重量份的无机填料和5-30重量份的包含热固性树脂和硬化剂的树脂组合物。 金属板被表面粗糙化或处理以至少在与复合树脂接触的一个表面上增强粘合力。 在本发明的电路基板中，复合树脂填充电路图案之间的空间，复合树脂组合物和金属板在用于安装部件的金属板侧形成一个平面。 在本发明的电路基板中，由于包含无机填料的树脂组合物也存在于金属板的电路图案之间的空间中，其散热特性极高，因此适用于电子设备的电路板 包含发电部件如电源电路。

公开(公告)号：US06487047B1

公开(公告)日：2002-11-26

申请号：US09324576

申请日：1999-06-02

Applicant: Arun Balakrishnan

Inventor： Arun Balakrishnan

IPC: G11B548

CPC classification number: G11B5/4853 ,  H05K1/024 ,  H05K2201/09236 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0597

Abstract: A tall-electrode trace interconnect array includes a dielectric support substrate for supporting least two tall-electrode trace conductors. A dielectric support structure on the support substrate supports outside longitudinal walls of the two tall-electrode trace conductors. The dielectric support structure is formed to be absent from a longitudinal space between the two tall-electrode trace conductors thereby defining an ambient air dielectric to reduce and control inter-electrode capacitance and increase resonant frequency and effective electrical bandwidth of the trace interconnect array. A method for forming the array is also disclosed.

Abstract translation: 高电极迹线互连阵列包括用于支撑最小二个高电极迹线导体的电介质支撑衬底。 支撑基板上的电介质支撑结构支撑两根高电极迹线导体的外侧纵向壁。 电介质支撑结构形成为不存在于两个高电极迹线导体之间的纵向空间中，从而限定环境空气电介质以减少并控制电极间电容并增加迹线互连阵列的谐振频率和有效电带宽。 还公开了一种形成阵列的方法。

公开(公告)号：US20020162685A1

公开(公告)日：2002-11-07

申请号：US10143713

申请日：2002-05-07

Inventor： Jeffrey Gotro ,  Karim Fernandes

IPC: H05K001/03 ,  H05K003/30 ,  H05K003/20

CPC classification number: H05K3/4626 ,  H05K2201/0195 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0759 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49155

Abstract: A multilayer circuit board comprising at least one substantially void free encapsulated heavy copper core and methods for producing such a board. Such a board may be formed by providing a first core that includes a substrate and heavy copper circuit traces, filling the spaces between circuit traces with a resin, and at least partially curing the resin so as to form two exposed and substantially planar surfaces on opposite sides of the core. The filled and planarized core is then laminated with additional dielectric layers to form a fully cured, void free multilayer printed circuit board.

Abstract translation: 包括至少一个基本上无空隙的封装重铜芯的多层电路板和用于制造这种板的方法。 这样的板可以通过提供包括基板和重铜电路迹线的第一芯体，用树脂填充电路迹线之间的空间，并且至少部分地固化树脂，从而在相对的两侧形成两个暴露的和基本平坦的表面 核心的一面。 然后将填充和平坦化的芯层与附加的电介质层层压以形成完全固化的无空隙的多层印刷电路板。

公开(公告)号：US06467161B2

公开(公告)日：2002-10-22

申请号：US09812989

申请日：2001-03-20

Applicant: Achyuta Achari ,  Brenda Joyce Nation ,  Delin Li ,  Lakhi N. Goenka ,  Richard Keith McMillan ,  Vivek A. Jairazbhoy

Inventor： Achyuta Achari ,  Brenda Joyce Nation ,  Delin Li ,  Lakhi N. Goenka ,  Richard Keith McMillan ,  Vivek A. Jairazbhoy

IPC: H05K320

CPC classification number: H05K3/4685 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method 10, 110 for making multi-layer electronic circuit boards 82, 148 having metallized apertures 18, 20, 118, 120 which may be selectively and electrically connected to a source of ground potential.

Abstract translation: 一种用于制造具有金属化孔18,20,118,120的多层电子电路板82,148的方法10,110，其可以选择性地和电连接到地电位源。

公开(公告)号：US20020060904A1

公开(公告)日：2002-05-23

申请号：US09961172

申请日：2001-09-24

Inventor： Kazuhito Higuchi

IPC: H05K007/02 ,  H05K007/06

CPC classification number: H05K3/4617 ,  H01L25/50 ,  H01L2224/83192 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H05K3/205 ,  H05K2201/0195 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2201/09963 ,  H05K2203/016 ,  H05K2203/1189

Abstract: An electronic component including an element main body section for performing an electrical function and a terminal section for electrically connecting the element main body section to a conductive member of an external device, the electronic component comprises a pair of sections arranged above the terminal section and opposite to each other in a stacking direction of the electronic component and a distance between the sections corresponding to a maximum thickness of the electronic component.

Abstract translation: 一种电子部件，包括用于执行电功能的元件主体部分和用于将元件主体部分电连接到外部装置的导电部件的端子部分，所述电子部件包括布置在所述端子部分上方的一对部分， 在电子部件的层叠方向上彼此相对的距离和对应于电子部件的最大厚度的部分之间的距离。

公开(公告)号：US20020034839A1

公开(公告)日：2002-03-21

申请号：US09994683

申请日：2001-11-28

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Hideki Iwaki ,  Yutaka Taguchi ,  Tetsuyoshi Ogura

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L021/4763 ,  H01L023/02 ,  H01L023/06 ,  H01L023/22 ,  H01L023/24 ,  H01L023/04 ,  H01L023/053 ,  H01L023/12

CPC classification number: H05K1/0251 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/024 ,  H05K1/0298 ,  H05K1/116 ,  H05K2201/0715 ,  H05K2201/09454 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09881 ,  H01L2924/00

Abstract: An insulator is provided between interconnect layers oppositely placed. The interconnect layers are connected between by connection members provided through the insulator. The connection members at one and the other ends are connected between in their center positions. A shield layer is provided spaced from the intermediate connection layer generally on a same plane as the intermediate connection layer. A condition of (Rnullr)/(2nullh)nullLnull(5nullRnullr)/h is satisfied, provided that a connection distance between the interconnect layers through the connection members and the intermediate connection layer is h, the connection members where considered generally as a circular cylinder have a diameter R, the intermediate connection layer where considered generally as circular has a diameter r, and a spaced distance between the intermediate connection layer and the shield layer is L. Thus, characteristic impedance is stabilized.

Abstract translation: 在相互布置的互连层之间设置绝缘体。 互连层通过通过绝缘体提供的连接构件连接在一起。 连接构件在一端和另一端连接在它们的中心位置之间。 屏蔽层设置成与中间连接层间隔开，通常在与中间连接层相同的平面上。 满足（Rr）/（2.h）<= L <=（5.Rr）/ h的条件，条件是通过连接构件和中间连接层的互连层之间的连接距离为h，连接 通常被认为是圆柱体的构件具有直径R，中间连接层通常被认为是圆形的，具有直径r，并且中间连接层和屏蔽层之间的间隔距离为L.因此，特性阻抗稳定。