公开(公告)号：US08854881B2

公开(公告)日：2014-10-07

申请号：US13858482

申请日：2013-04-08

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C11/34 ,  G11C13/00 ,  G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  B82Y30/00

CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract translation: 本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为通过在存储器操作期间调整存取信号来补偿存储器层中的参数变化。 在一些实施例中，存储器单元基于第三维存储器技术。 在至少一些实施例中，集成电路包括多层存储器，包括半导体材料子层的层。 集成电路还包括被配置为生成访问信号以便于访问操作的访问信号发生器，以及被配置为调整多层存储器中的每层的访问信号的特征调整器。

公开(公告)号：US20140009998A1

公开(公告)日：2014-01-09

申请号：US14023233

申请日：2013-09-10

Applicant: Unity Semiconductor Corporation

Inventor： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Rene Meyer

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

公开(公告)号：US20040228172A1

公开(公告)日：2004-11-18

申请号：US10605977

申请日：2003-11-11

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Darrell Rinerson ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward ,  Christophe J. Chevallier

IPC: G11C011/00

CPC classification number: H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

Abstract translation: 提供导电存储器堆叠。 存储器堆叠包括底部电极，顶部电极和多电阻状态元件。 多电阻状态元件被夹在电极之间，使得底部电极的顶面与多电阻状态元件的底面接触，并且顶部电极的底面与多电阻状态元件的底面接触 顶面。 底部电极，顶部电极和多电阻状态元件都具有与其表面相邻的侧面。 此外，侧面至少部分地被侧壁层覆盖。

公开(公告)号：US20040160819A1

公开(公告)日：2004-08-19

申请号：US10360005

申请日：2003-02-07

Applicant: Unity Semiconductor Corporation

Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Wayne Kinney

IPC: G11C011/14

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77

Abstract: High density NVRAM. The invention is a an array of memory cells capable of storing at least a megabit of information, each memory cell including a memory plug that includes a memory element that switches from a first resistance state to a second resistance state upon application of a first write voltage of a first polarity and reversibly switches from the second resistance state to the first resistance state upon application of a second write voltage of polarity opposite to the first polarity.

Abstract translation: 高密度NVRAM。 本发明是能够存储至少一百万个信息的存储器单元的阵列，每个存储单元包括一个存储器插头，该存储器插件包括一个存储元件，该存储器元件在施加第一写入电压时从第一电阻状态切换到第二电阻状态 第一极性的第二写入电压与第一极性相反的第二写入电压可逆地从第二电阻状态切换到第一电阻状态。

公开(公告)号：US12074400B1

公开(公告)日：2024-08-27

申请号：US18630700

申请日：2024-04-09

Applicant: Unity Semiconductor

Inventor： Yueh Sheng Ow ,  Mayeul Durand de Gevigney ,  Christophe Isnard

IPC: H01R31/06 ,  H01R12/71

CPC classification number: H01R31/06 ,  H01R12/716

Abstract: An adapter for retaining a wafer has a back side intended to be placed on, and to extend over, a first suction channel and a second suction channel disposed on a main face of a support. The adapter has a shallow recess disposed on the front side to receive the wafer, the shallow recess being shaped to the wafer size and having a flat base to contact a surface of the wafer. The adapter also includes a vacuum network extending through the adapter and comprising at least one through-passage connecting the adapter back side and the adapter front side, the through-passage opening out, on the front side, in the shallow recess. The through-passage intercepts, on the back side, the first suction channel of the support but not the second suction channel.

公开(公告)号：US11965834B2

公开(公告)日：2024-04-23

申请号：US17283686

申请日：2019-09-20

Applicant: Unity Semiconductor

Inventor： Mayeul Durand de Gevigney

IPC: G01N21/88 ,  G01N21/47 ,  G01N21/95

CPC classification number: G01N21/8806 ,  G01N21/474 ,  G01N21/9501 ,  G01N21/9506 ,  G01N2021/4707 ,  G01N2021/4709 ,  G01N2021/4742 ,  G01N2021/8822

Abstract: A device for dark-field optical inspection of a substrate comprises: a light source for generating an incident beam that is projected onto an inspection zone of the substrate and that is capable of being reflected in the form of diffuse radiation; at least one first and one second collecting device; and a reflecting device for directing at least a portion of the diffuse radiation originating from a focal point of collection coincident with the inspection zone in the direction of the collecting devices, with a first and second reflective zone from which a first portion of the diffuse radiation is directed toward a first focal point, which is optically conjugated with the focal point of collection, and a second portion of the diffuse radiation is reflected toward a second focal point, which is optically conjugated with the collection focal point and distinct from the first focal point of detection.

公开(公告)号：US20230377121A1

公开(公告)日：2023-11-23

申请号：US18319281

申请日：2023-05-17

Applicant: UNITY SEMICONDUCTOR

Inventor： Wolfgang Alexander IFF ,  Alain COURTEVILLE

IPC: G06T7/00 ,  B81C99/00 ,  G06T7/521 ,  G06T7/60 ,  G01B11/22

CPC classification number: G06T7/0004 ,  B81C99/003 ,  G06T7/521 ,  G06T7/60 ,  G01B11/22 ,  G06T2207/30148

Abstract: A method for characterizing structures etched in a substrate, such as a wafer is disclosed. The method includes the following steps: illuminating the bottom of at least one structure with an illumination beam issued from a light source emitting light with a wavelength adapted to be transmitted through the substrate, acquiring, with an imaging device positioned on the bottom side of said substrate, at least one image of a bottom of the at least one structure through the substrate, and measuring at least one data, called lateral data, relating to a lateral dimension of the bottom of the at least one HAR structure from the at least one acquired image. A system implementing such a method is also disclosed.

公开(公告)号：US20230251079A1

公开(公告)日：2023-08-10

申请号：US18302151

申请日：2023-04-18

Applicant: UNITY SEMICONDUCTOR

Inventor： Jean-François BOULANGER ,  Isabelle BERGOËND

IPC: G01B9/0209 ,  G01B9/02 ,  G01B11/06

CPC classification number: G01B9/0209 ,  G01B9/02083 ,  G01B11/0625 ,  G01B9/02088 ,  G01B2210/56

Abstract: A method and related system for measuring a surface of a substrate including at least one structure using low coherence optical interferometry, the method being implemented with a system having an interferometric device, a light source, an imaging sensor, and a processing module, and including: —acquiring, with the imaging sensor, an interferometric signal formed by the interferometric device between a reference beam and a measurement beam reflected by the surface at a plurality of measurement points in a field of view; the following steps being carried out by the processing module:



classifying, by a learning technique, the acquired interferometric signals according to a plurality of classes, each class being associated with a reference interferometric signal representative of a typical structure; and
analysing the interferometric signals to derive therefrom information on the structure at the measurement points, as a function of the class of each interferometric signal.

公开(公告)号：US20220392956A1

公开(公告)日：2022-12-08

申请号：US17840385

申请日：2022-06-14

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman

IPC: H01L27/24 ,  H01L45/00

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US11011226B2

公开(公告)日：2021-05-18

申请号：US16838423

申请日：2020-04-02

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/21

Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.