公开(公告)号：US20140191396A1

公开(公告)日：2014-07-10

申请号：US14205880

申请日：2014-03-12

Applicant: MEDIA TEK INC.

Inventor： Tzu-Hung LIN ,  Wen-Sung HSU ,  Ta-Jen YU ,  Andrew C. CHANG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/48 ,  H01L23/49541 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L28/00 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/3224 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace.

Abstract translation: 在一种配置中，半导体封装包括嵌入在基底中的导电迹线和通过导电结构安装在导电迹线上的半导体器件，其中导电结构是凸块结构，并且凸块结构的宽度大于 导电迹线。 在另一种结构中，制造半导体封装的方法包括提供基底，在基底上形成至少一个导电迹线，在基底上形成额外的绝缘材料，并在附加绝缘材料上限定图案，其中图案形成在 至少一个导电迹线，其中所述导电结构是凸块结构，并且所述凸块结构的宽度大于所述导电迹线的宽度。

公开(公告)号：US20140097004A1

公开(公告)日：2014-04-10

申请号：US14096514

申请日：2013-12-04

Applicant: PANASONIC CORPORATION

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA

IPC: H05K1/11

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Abstract translation: 提供其中在表面上设置布线的三维结构。 三维结构的表面的至少一部分包括含有填料的绝缘层。 在三维结构的表面上设置用于布线的凹槽，并且布线导体的至少一部分嵌入到凹槽中用于布线。

公开(公告)号：US20140090876A1

公开(公告)日：2014-04-03

申请号：US14096504

申请日：2013-12-04

Applicant: PANASONIC CORPORATION

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA

IPC: H05K1/11

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A three-dimensional structure in which a wiring and a pad part are provided on a surface is provided. A recessed gutter for wiring and a hole for the pad part having a depth that is greater than a thickness of the recessed gutter for wiring are provided on the surface of the three-dimensional structure. The hole for the pad part is provided in succession with the recessed gutter for wiring. At least a part of a wiring conductor is embedded in the recessed gutter for wiring and in the hole for the pad part.

Abstract translation: 提供了其中在表面上设置布线和焊盘部分的三维结构。 在三维结构的表面上设置用于布线的凹槽和用于焊盘部分的孔，其深度大于用于布线的凹槽的厚度。 用于焊盘部分的孔连续地设置有用于布线的凹槽。 布线导体的至少一部分嵌入到用于布线的凹槽中和用于垫部的孔中。

公开(公告)号：US08621748B2

公开(公告)日：2014-01-07

申请号：US12574287

申请日：2009-10-06

Applicant: Michimasa Takahashi ,  Yukinobu Mikado ,  Hiroyuki Yanagisawa

Inventor： Michimasa Takahashi ,  Yukinobu Mikado ,  Hiroyuki Yanagisawa

IPC: H05K3/30

CPC classification number: H05K1/167 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/1453

Abstract: A manufacturing method of a printed wiring board, including forming a plurality of electrodes on a conductive layer formed on a substrate by a plating method, forming an insulation layer on the electrodes and the conductive layer, removing the substrate from the conductive layer, patterning the conductive layer except for a resistor forming region reserved for forming a resistor, thereby forming an external connection conductive pattern, and forming a resistor in the resistor forming region such that the resistor is separated by a space from the external connection conductive pattern.

Abstract translation: 一种印刷电路板的制造方法，其特征在于，在电镀形成于基板上的导电层上形成多个电极，在所述电极和所述导电层上形成绝缘层，从所述导电层除去所述基板， 导电层除了保留用于形成电阻器的电阻器形成区域，从而形成外部连接导电图案，并且在电阻器形成区域中形成电阻器，使得电阻器与外部连接导电图案间隔开。

公开(公告)号：US08607448B2

公开(公告)日：2013-12-17

申请号：US13621122

申请日：2012-09-15

Applicant: Heung-Kyu Kim

Inventor： Heung-Kyu Kim

IPC: H01K3/10

CPC classification number: H01P3/081 ,  H01P11/003 ,  H05K1/0221 ,  H05K3/205 ,  H05K2201/0376 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09827

Abstract: A printed circuit board having a micro strip line, a printed circuit board having a strip line and a method of manufacturing thereof are disclosed. The printed circuit board having a micro strip line in accordance with an embodiment of the present invention includes a first insulation layer, a signal line buried in one surface of the first insulation layer, a plurality of conductors penetrating through the first insulation layer and being disposed on both sides of the signal line in parallel with the signal line, and a ground layer formed to be electrically connected to the conductor on the other surface of the first insulation layer.

Abstract translation: 公开了一种具有微带线的印刷电路板，具有带状线的印刷电路板及其制造方法。 根据本发明实施例的具有微带线的印刷电路板包括第一绝缘层，埋在第一绝缘层的一个表面中的信号线，穿过第一绝缘层并被布置的多个导体 在与信号线并联的信号线的两侧，以及形成为与第一绝缘层的另一个表面上的导体电连接的接地层。

公开(公告)号：US08552570B2

公开(公告)日：2013-10-08

申请号：US12811733

申请日：2009-01-06

Applicant: Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

Inventor： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

IPC: H01L29/40

CPC classification number: H05K3/4647 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2203/0733 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.

Abstract translation: 在布线板中，绝缘层和布线层交替层叠，并且布线层通过通孔电连接。 布线基板包括布置在第一表面中并嵌入绝缘层中的第一端子，布置在与第一表面相对的第二表面中并嵌入绝缘层中的第二端子，以及布置在绝缘层中并与第一端子接触的焊盘 终端。 通孔将焊盘和与绝缘层交替层压的布线层电连接。 在接地侧的每个通孔的端部没有形成连接接口，但是在布线层侧的每个通孔的端部形成有连接接口。

公开(公告)号：US20130235543A1

公开(公告)日：2013-09-12

申请号：US13873504

申请日：2013-04-30

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Junichi Nakamura ,  Yuji Kobayashi

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/116 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2203/0338 ,  H05K2203/0361 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.

Abstract translation: 制造布线板的方法包括在支撑板上形成限定开口部分的焊料或电镀抗蚀剂层的抗蚀剂层，使得支撑板的一部分露出。 电极直接形成在开口部内的支撑板上，当使用时，电镀抗蚀剂层被去除。 在电极以及支撑板或阻焊层上形成绝缘层，并且还形成连接到绝缘层处的电极的布线部分。 然后在布线部分上形成具有开口部分的阻焊层，并且去除支撑板以暴露电极的表面或电极和绝缘层的表面。 然后可以在绝缘层的暴露表面上形成具有开口部分的另一阻焊层。

公开(公告)号：US20130235535A1

公开(公告)日：2013-09-12

申请号：US13870199

申请日：2013-04-25

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Kazuhiro ISEBO

IPC: H05K1/03 ,  H05K3/00

CPC classification number: H05K1/0306 ,  H05K1/11 ,  H05K3/0044 ,  H05K3/28 ,  H05K3/284 ,  H05K3/4007 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09527 ,  H05K2201/098 ,  Y10T29/4916

Abstract: A composite substrate includes a ceramic substrate including, on at least one surface, a circuit wire on which an electronic component is to be mounted, a plurality of external connection terminals provided on one surface of the ceramic substrate, and a resin layer provided on the one surface of the ceramic substrate. The external connection terminals have a cross sectional area that decreases with increasing distance from the one surface of the ceramic substrate, and end surfaces of the external connection terminals opposite to end surfaces connected to the ceramic substrate are partially or entirely exposed from the resin layer.

Abstract translation: 复合基板包括陶瓷基板，该陶瓷基板在至少一个表面上包括将要安装电子部件的电路线，设置在陶瓷基板的一个表面上的多个外部连接端子和设置在该陶瓷基板上的树脂层 陶瓷基板的一个表面。 外部连接端子的横截面积随陶瓷基板的一个表面的距离的增加而减小，与陶瓷基板连接的端面相对的外部连接端子的端面部分或全部从树脂层露出。

公开(公告)号：US08389398B2

公开(公告)日：2013-03-05

申请号：US13431816

申请日：2012-03-27

Applicant: KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

Inventor： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC: H01L21/44

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A method of making a semiconductor device comprises providing a carrier, forming a first conductive layer extending above a surface of the carrier, providing a substrate, disposing the first conductive layer into a first surface of the substrate, removing the carrier, forming a second conductive layer extending above the first surface of the substrate to create a vertical offset between the first conductive layer and second conductive layer, and forming a plurality of first bumps over the first conductive layer and second conductive layer. The method further includes the steps of disposing a third conductive layer into a second surface of the substrate opposite the first surface of the substrate, forming a fourth conductive layer extending above the second surface of the substrate to create a vertical offset between the third conductive layer and fourth conductive layer, and forming a plurality of second bumps.

Abstract translation: 制造半导体器件的方法包括提供载体，形成在载体的表面上延伸的第一导电层，提供衬底，将第一导电层设置在衬底的第一表面中，去除载体，形成第二导电 层，其在所述基板的所述第一表面上方延伸以在所述第一导电层和所述第二导电层之间产生垂直偏移，以及在所述第一导电层和所述第二导电层上形成多个第一凸块。 该方法还包括以下步骤：将第三导电层设置在与衬底的第一表面相对的衬底的第二表面中，形成在衬底的第二表面之上延伸的第四导电层，以在第三导电层 和第四导电层，并形成多个第二凸块。

公开(公告)号：US08373071B2

公开(公告)日：2013-02-12

申请号：US12696629

申请日：2010-01-29

Applicant: Cheng-Po Yu ,  Chai-Liang Hsu

Inventor： Cheng-Po Yu ,  Chai-Liang Hsu

IPC: H05K1/00

CPC classification number: H05K3/107 ,  H05K3/181 ,  H05K3/422 ,  H05K2201/0376

Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed, in which the activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.

Abstract translation: 提供了一种用于制造嵌入式布线板的方法。 形成激活绝缘层，其中活化绝缘层包括多个催化剂颗粒，并覆盖第一布线层。 在活化绝缘层上形成凹版图案和部分露出第一布线层的至少一个盲孔，其中一些催化剂颗粒被活化并以凹版图案和盲孔曝光。 将激活绝缘层浸入第一化学镀溶液中，并通过化学镀在盲孔中形成固体导电柱。 在形成固体导电柱之后，将激活绝缘层浸入第二化学镀溶液中，并且通过无电解电镀在凹版图案中形成第二布线层。 第一化学镀液和第二化学镀液的成分不同。