公开(公告)号：US20090031062A1

公开(公告)日：2009-01-29

申请号：US12175466

申请日：2008-07-18

Applicant: Cheng-Lai Shen ,  Yueh-Chih Chen ,  Pei-Hua Sun ,  Chung-Ta Chin

Inventor： Cheng-Lai Shen ,  Yueh-Chih Chen ,  Pei-Hua Sun ,  Chung-Ta Chin

IPC: G06F13/00

CPC classification number: G06F13/409 ,  H05K1/142 ,  H05K2201/044 ,  H05K2201/10189

Abstract: A modularized motherboard is provided. The modularized motherboard includes a first circuit board, a second circuit board and a connecting device. The first circuit board includes a north bridge chip, a central processing unit (CPU) slot and a first connecting port. The CPU slot is coupled to the north bridge chip and is used for installing a CPU. The second circuit board is independent of the first circuit board. The second circuit board includes a second connecting port and a south bridge chip. The south bridge chip is coupled to the north bridge chip via the second connecting port the first connecting port. The connecting device is coupled between the first connecting port and the second connecting port.

Abstract translation: 提供模块化主板。 模块化主板包括第一电路板，第二电路板和连接装置。 第一电路板包括北桥芯片，中央处理单元（CPU）插槽和第一连接端口。 CPU插槽与北桥芯片相连，用于安装CPU。 第二个电路板独立于第一个电路板。 第二电路板包括第二连接端口和南桥芯片。 南桥芯片通过第二连接端口连接到北桥芯片的第一连接端口。 连接装置连接在第一连接端口和第二连接端口之间。

公开(公告)号：US07478287B2

公开(公告)日：2009-01-13

申请号：US11270608

申请日：2005-11-10

Applicant: Seiji Funaba ,  Yoji Nishio

Inventor： Seiji Funaba ,  Yoji Nishio

IPC: G11B20/20 ,  G01R31/28 ,  G01R31/26

CPC classification number: G11C7/22 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H05K1/0248 ,  H05K1/0268 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09781

Abstract: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

Abstract translation: 虚拟布线25用于模拟连接电路板上的半导体集成电路2和6的实际布线26。 半导体集成电路包括能够可变地设置转换速率的数据输出电路28和用于使用虚拟布线25测量信号发送点和信号反射点之间的信号延迟时间的电路29（特征阻抗失配点），并且 由测量电路获得的延迟时间用于确定输出电路的信号转换时间。 信号的转换时间设置为信号发送点和最近端的布线支路之间的信号延迟时间的至少两倍。 以这种方式，实现了由最近端的反射点减轻反射的信号传输。

公开(公告)号：US20080318454A1

公开(公告)日：2008-12-25

申请号：US11766204

申请日：2007-06-21

Applicant: Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

Inventor： Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

IPC: H01R12/16

CPC classification number: H05K1/0271 ,  H05K2201/044 ,  H05K2201/09063 ,  H05K2201/10409 ,  H05K2201/10734

Abstract: An information handling system circuit board has an opening formed through it proximate a coupling point of an integrated circuit to the circuit board. The opening manages stress at the coupling point of the integrated circuit to the circuit board to reduce the risk of damage to the coupling point during deformation of the circuit board, such as when the circuit board is coupled to a chassis or when a component is pressed into the circuit board. In one embodiment, rectangular openings are formed at diagonally opposed corners of a BSA integrated circuit. In alternative embodiments, openings of varying shape, such as slots or curved slots, are formed at selected corners of the integrated circuit.

Abstract translation: 信息处理系统电路板具有通过其形成的开口，其靠近集成电路到电路板的耦合点。 开口处理集成电路到电路板的耦合点处的应力，以减少在电路板变形期间对耦合点的损坏的风险，例如当电路板耦合到底盘或当部件被按压时 进入电路板。 在一个实施例中，在BSA集成电路的对角相对的角上形成矩形开口。 在替代实施例中，在集成电路的选定角处形成变化形状的开口，例如槽或弯曲槽。

公开(公告)号：US20080298035A1

公开(公告)日：2008-12-04

申请号：US12222232

申请日：2008-08-05

Applicant: Naohiko Kajio ,  Masaki Yoshimaru

Inventor： Naohiko Kajio ,  Masaki Yoshimaru

IPC: H05K1/11

CPC classification number: H05K7/1492 ,  H05K1/0263 ,  H05K1/14 ,  H05K1/141 ,  H05K1/148 ,  H05K2201/044 ,  H05K2201/10272 ,  H05K2201/10287

Abstract: A second printed wiring board is opposed to a surface of the first printed wiring board. A support member supports the first and second printed wiring boards. A first connector is mounted on the first printed wiring board. A second connector is mounted on the second printed wiring board. A wiring connects the first printed wiring board to the second printed wiring board. The first and second connectors are separately mounted on the first and second printed wiring boards, respectively. The sizes of the first and second printed wiring boards can be reduced as compared with the case where connectors are arranged in a row on a single printed wiring board, for example. This results in a reduction in the size of the printed circuit board unit. A large number of the printed circuit board units can be coupled to the back panel.

Abstract translation: 第二印刷线路板与第一印刷线路板的表面相对。 支撑构件支撑第一和第二印刷线路板。 第一连接器安装在第一印刷线路板上。 第二连接器安装在第二印刷线路板上。 布线将第一印刷布线板连接到第二印刷布线板。 第一和第二连接器分别安装在第一和第二印刷电路板上。 与在单个印刷电路板上连接成排配置的情况相比，可以减小第一和第二印刷电路板的尺寸。 这导致印刷电路板单元的尺寸的减小。 大量印刷电路板单元可以耦合到后面板。

公开(公告)号：US20080270649A1

公开(公告)日：2008-10-30

申请号：US11799169

申请日：2007-04-30

Applicant: Roger A. Pearson ,  Shane Ward

Inventor： Roger A. Pearson ,  Shane Ward

IPC: G06F13/00

CPC classification number: G06F13/409 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/045 ,  H05K2201/10159

Abstract: A multi-channel memory connection system comprises a circuit board comprising a plurality of memory connectors, at least one of the plurality of memory connectors configured to receive either a memory module or a memory riser, the at least one memory connector having at least two memory channels connected thereto through the circuit board.

Abstract translation: 多通道存储器连接系统包括包括多个存储器连接器的电路板，所述多个存储器连接器中的至少一个被配置为接收存储器模块或存储器提升器，所述至少一个存储器连接器具有至少两个存储器 通过电路板与其连接的通道。

公开(公告)号：US07422484B2

公开(公告)日：2008-09-09

申请号：US11522530

申请日：2006-09-18

Applicant: Thomas S. Cohen ,  Marc B. Cartier, Jr. ,  Mark W. Gailus

Inventor： Thomas S. Cohen ,  Marc B. Cartier, Jr. ,  Mark W. Gailus

IPC: H01R13/648

CPC classification number: H05K7/1445 ,  H01R13/514 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

Abstract translation: 中平面具有连接第一差分连接器的接触端的第一侧和与第二差分连接器的接触端连接的第一侧相对的第二侧。 中平面包括从第一侧延伸到第二侧的多个通孔，其中通孔在第一侧上提供第一信号发射，而第二信号在第二侧上发射。 第一信号发射被设置成多行，每行具有沿着第一线的第一信号发射，并且第一信号沿着基本上平行于第一线的第二线发射。 第二信号发射被提供在多列中，每列具有沿着第三线的第二信号发射，而第二信号沿着基本上平行于第三线的第四线发射。

公开(公告)号：US07405947B1

公开(公告)日：2008-07-29

申请号：US11809595

申请日：2007-06-01

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01R12/16

CPC classification number: H05K1/0237 ,  H05K1/0219 ,  H05K1/0225 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09663

Abstract: For electrical backplanes and the like, a power plane adaptation to improve the propagation of high-speed signals through clearances in an embedded power plane is disclosed. In exemplary embodiments, the power plane is segmented in a high-speed connector region, such that a portion of the metal layer that forms the power plane is retained in the high-speed connector region—but isolated from the power-delivery portion of the power plane. The isolated portion is connected to digital ground, and clearances are formed therein where high-speed signaling throughholes will pass through the region. In some embodiments, various attainable advantages include better manufacturability, better matching and control of high-speed signaling throughhole impedance, and improved noise isolation. Other embodiments are described and claimed.

Abstract translation: 对于电气背板等，公开了一种用于改进高速信号通过嵌入式电源平面中的间隙的传播的电力平面适配。 在示例性实施例中，电力平面在高速连接器区域中被分段，使得形成电力平面的金属层的一部分保持在高速连接器区域中，但是与电力输送部分 电力飞机 隔离部分连接到数字地，并且在其中形成间隙，其中高速信令通孔将通过该区域。 在一些实施例中，各种可获得的优点包括更好的可制造性，更好地匹配和控制高速信号通孔阻抗以及改进的噪声隔离。 描述和要求保护其他实施例。

公开(公告)号：US20080112133A1

公开(公告)日：2008-05-15

申请号：US11933977

申请日：2007-11-01

Applicant: Ola Torudbakken ,  Andreas Bechtolsheim ,  Gilberto Figuera ,  Hon Hung Yam

Inventor： Ola Torudbakken ,  Andreas Bechtolsheim ,  Gilberto Figuera ,  Hon Hung Yam

IPC: H05K7/04 ,  H05K7/20

CPC classification number: H05K1/14 ,  H04Q1/03 ,  H04Q1/035 ,  H04Q1/04 ,  H04Q1/06 ,  H04Q1/08 ,  H05K7/1445 ,  H05K2201/044 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A switch chassis includes a plane having pass-through vias. An array of connector pairs is provided. A connector pair includes a first multi-path connector on first side of the plane and a second multi-path connector on the second side of the plane interconnected through the pass-through vias in the plane. Fabric cards can be connected to respective columns of first connectors and line cards can be connected respective rows of second connectors of the connector pairs to orient the fabric and lines cards orthogonally with respect to each other.

Abstract translation: 开关底盘包括具有通孔的平面。 提供一组连接器对。 连接器对包括在平面的第一侧上的第一多路径连接器和在平面的通过通孔互连的平面的第二侧上的第二多路径连接器。 织物卡可以连接到第一连接器的相应列，并且线卡可连接连接器对的相应行的第二连接器，以使织物和线卡相对于彼此正交地定向。

公开(公告)号：US20080101049A1

公开(公告)日：2008-05-01

申请号：US11586912

申请日：2006-10-26

Applicant: Brian W. Casto ,  John J. Retterer ,  Thomas L. Smith

Inventor： Brian W. Casto ,  John J. Retterer ,  Thomas L. Smith

IPC: H01R12/16

CPC classification number: H05K1/14 ,  G06F1/18 ,  H05K1/144 ,  H05K2201/044 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/10189

Abstract: In one exemplary embodiment, a system for supplying electrical connectivity to one or more circuit board based devices includes a backplane and at least one module. The backplane includes a mounting surface having a plurality of modular power connectors. The at least one module includes an interface portion, a power connection portion, and a circuit board. The power connection portion is configured to connect with the corresponding one of the plurality of modular power connectors. The circuit board includes a plurality of power-related electrical contacts and a plurality of data-related electrical contacts. At least one of the plurality of power-related electrical contacts is connected with the power connection portion, and at least one of the plurality of data-related electrical contacts is connected with the interface portion. The backplane is configured to connect with a power supply, such that the power supply supplies power to the at least one module through one of the modular power connectors when the at least one module is connected with the corresponding modular power connector.

Abstract translation: 在一个示例性实施例中，用于向一个或多个基于电路板的设备提供电连接的系统包括背板和至少一个模块。 背板包括具有多个模块化电源连接器的安装表面。 所述至少一个模块包括接口部分，电源连接部分和电路板。 电源连接部分被配置为与多个模块化电源连接器中的相应一个连接。 电路板包括多个功率相关的电触点和多个数据相关的电触点。 所述多个功率相关的电触头中的至少一个与所述电源连接部分连接，并且所述多个与数据有关的电触点中的至少一个与所述接口部分连接。 背板被配置为与电源连接，使得当至少一个模块与相应的模块化电源连接器连接时，电源通过模块化电源连接器之一向至少一个模块供电。

公开(公告)号：US20080075070A1

公开(公告)日：2008-03-27

申请号：US11978810

申请日：2007-10-30

Applicant: Joel Goergen

Inventor： Joel Goergen

IPC: H04L12/50

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: A circuit board comprises signaling through-holes that pass through a plurality of layers, including signal trace and digital ground plane layers, and power reference plane layers. Clearances are set to achieve a desired impedance characteristic for the through-holes. At a power reference plane layer, the clearance is defined around multiple neighboring through-holes.

Abstract translation: 电路板包括通过多个层的信令通孔，包括信号迹线和数字接地层以及功率参考平面层。 设定间隙以实现通孔所需的阻抗特性。 在功率参考平面层上，间隙围绕多个相邻的通孔限定。