公开(公告)号：US5829126A

公开(公告)日：1998-11-03

申请号：US638038

申请日：1996-04-26

Applicant: Koichi Nagao ,  Yoshiro Nakata ,  Shinichi Oki

Inventor： Koichi Nagao ,  Yoshiro Nakata ,  Shinichi Oki

IPC: G01R31/26 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  H01L21/66 ,  H05K3/40 ,  H05K3/42 ,  H01R9/00

CPC classification number: G01R1/06738 ,  G01R1/06761 ,  G01R3/00 ,  H05K3/4007 ,  G01R1/07307 ,  H01R12/714 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0278 ,  H05K2203/1152 ,  H05K3/423 ,  Y10T29/49004 ,  Y10T29/49149

Abstract: Bumps to be connected to inspection electrodes of semiconductor chips are formed on a surface of a flexible substrate. A plating layer is formed which is made of a harder material than the bumps formed on the flexible substrate and which has a concave portion or a convex portion whose diameter is equal to or smaller than half the diameter of the bumps, on a flat metallic plate. The plating layer of the metallic plate is pressed against top surfaces of the bumps, so that irregularities are formed in the top surfaces of the bumps.

Abstract translation: 在柔性基板的表面上形成要连接到半导体芯片的检查电极的凸起。 形成电镀层，该镀层比形成在柔性基板上的凸点更硬的材料制成，并且在平坦的金属板上具有直径等于或小于凸块的直径的一半的凹部或凸部 。 金属板的镀层被压在凸块的顶表面上，从而在凸块的顶表面上形成凹凸。

公开(公告)号：US5815000A

公开(公告)日：1998-09-29

申请号：US580687

申请日：1995-12-29

Applicant: Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree ,  Salman Akram

Inventor： Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree ,  Salman Akram

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/42 ,  G01R31/02

CPC classification number: G01R1/0466 ,  G01R1/0483 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/80 ,  H01L24/85 ,  H05K3/4007 ,  G01R3/00 ,  G01R31/2863 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2225/06562 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

Abstract: A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.

Abstract translation: 提供了一种用于封装和测试半导体管芯的方法。 该方法包括形成具有与常规塑料或陶瓷半导体封装相同的尺寸，形状和引线配置的裸片的临时封装。 临时包装可用于使用标准设备对模具进行老化测试。 然后可以将模具从包装中取出并被认证为已知的好的模具。 在说明性实施例中，封装形成为SOJ构造。 该包装包括底座，互连和力施加机构。 封装基底可以使用陶瓷层压工艺或Cerdip形成工艺由陶瓷或塑料制成。

公开(公告)号：US5776824A

公开(公告)日：1998-07-07

申请号：US577187

申请日：1995-12-22

Applicant: Warren M. Farnworth ,  David R. Hembree

Inventor： Warren M. Farnworth ,  David R. Hembree

IPC: H01L21/48 ,  H05K3/00 ,  H05K3/06 ,  H05K3/40 ,  H05K3/42 ,  H01L21/441

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/135 ,  H05K3/002 ,  H05K3/064 ,  H05K3/423 ,  Y02P80/30 ,  Y10S428/901 ,  Y10T428/31681

Abstract: A process for producing laminated film/metal structures comprising bumped circuit traces on a non-conductive substrate wherein a copper sheet/polyimide film laminate is coated with resist on the exterior surfaces. The resist adjacent the polyimide film is selectively exposed and etched to expose an area of the polyimide film. The exposed polyimide film is etched to form vias through the polyimide film to the inner side of the copper sheet. The resist adjacent the polyimide film is stripped away and a metal bump is electrolytically plated through each via onto the copper sheet. A subsequent layer of resist is electrophoretically applied over the bumps. The resist material adjacent the copper sheet is then selectively exposed and etched to expose areas of the copper sheet. The exposed copper sheet is etched to form circuit traces and the remaining resist adjacent both the polyimide film and the copper sheet is stripped away.

Abstract translation: 一种在非导电性基板上形成有凸起电路迹线的叠层膜/金属结构体的制造方法，其中铜片/聚酰亚胺膜层叠体在外表面上涂有抗蚀剂。 选择性地暴露和蚀刻邻近聚酰亚胺膜的抗蚀剂以暴露聚酰亚胺膜的区域。 蚀刻暴露的聚酰亚胺膜，以通过聚酰亚胺膜形成通孔至铜片的内侧。 剥离与聚酰亚胺膜相邻的抗蚀剂，并通过每个通孔将金属凸块电镀到铜片上。 随后的抗蚀剂层电泳施加在凸块上。 然后选择性地暴露和蚀刻邻近铜片的抗蚀剂材料以暴露铜片的区域。 将曝光的铜片蚀刻以形成电路迹线，并将与聚酰亚胺膜和铜片相邻的剩余抗蚀剂剥离。

公开(公告)号：US5342807A

公开(公告)日：1994-08-30

申请号：US976093

申请日：1992-11-13

Applicant: Larry D. Kinsman ,  Derek J. Gochnour ,  Alan G. Wood ,  Warren M. Farnworth

Inventor： Larry D. Kinsman ,  Derek J. Gochnour ,  Alan G. Wood ,  Warren M. Farnworth

IPC: G01R1/04 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC classification number: G01R1/0466 ,  G01R1/0483 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/85 ,  H05K3/4007 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2863 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85001 ,  H01L2224/85099 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85214 ,  H01L2225/06562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/16195 ,  H01L2924/20751 ,  H01L2924/20753 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423 ,  Y10S228/904 ,  Y10T29/49004

Abstract: On a semiconductor integrated circuit die, a semipermanent electrical connection is effected by the use of wirebond techniques, in which the parameters of the wirebond are controlled, so that less bonding force retains the leadwires to the bondpads than the attachment strength of the bondpads to the die. The wirebond techniques include attaching leadwires to bondpads on the die, using ultrasonic wedge bonding. The strength of the bond between the leadwires is significantly less than the attachment strength of the bondpads, preferably by a ratio which ensures that the bondpads are not lifted from the die when the leadwires are removed by breaking the bond between the leadwires and the bondpads. Subsequent to testing and burnin, the bond between the leadwires and the bondpads is severed. The die are then removed from the package body and the bondpads may then be attached by conventional means. The technique is useful in providing known good die.

Abstract translation: 在半导体集成电路管芯上，通过使用引线接合技术来实现半永久性电连接，其中引线键合的参数被控制，使得较少的结合力将导线保持在粘合垫上，而不是粘合垫的附着强度 死。 引线接合技术包括使用超声波楔形接合将引线连接到管芯上的焊盘。 引线之间的结合强度显着小于粘合垫的附着强度，优选地通过确保当引线通过断开引线和粘合垫之间的键而去除引线时，粘合垫不会从模具上提起的比例。 在测试和燃烧之后，引线和焊盘之间的接合被切断。 然后将模具从包装体中取出，然后可以通过常规方法将粘合垫连接起来。 该技术在提供已知的好的模具中是有用的。

公开(公告)号：US5336649A

公开(公告)日：1994-08-09

申请号：US976221

申请日：1992-11-13

Applicant: Larry D. Kinsman ,  Derek J. Gochnour ,  Alan G. Wood ,  Warren M. Farnworth

Inventor： Larry D. Kinsman ,  Derek J. Gochnour ,  Alan G. Wood ,  Warren M. Farnworth

IPC: G01R1/04 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC classification number: G01R1/0466 ,  G01R1/0483 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/85 ,  H05K3/4007 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2863 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85001 ,  H01L2224/85099 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85214 ,  H01L2225/06562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/16195 ,  H01L2924/20751 ,  H01L2924/20753 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

Abstract: In order to provide pretested bare semiconductor integrated circuit die, a temporary mechanical connection is effected by the use of a soluble material. A semipermanent electrical connection is effected, in which the parameters of the connection are controlled, so that the die remains functional subsequent to burnin and test. Subsequent to testing and burnin, the die are removed from the package body. The technique is useful in providing known good die.

Abstract translation: 为了提供预先测试的裸半导体集成电路管芯，通过使用可溶性材料实现临时机械连接。 进行半永久电连接，其中连接的参数被控制，使得模具在燃烧和测试之后保持功能。 在测试和燃烧之后，将模具从包装体中取出。 该技术在提供已知的好的模具中是有用的。

公开(公告)号：US4184729A

公开(公告)日：1980-01-22

申请号：US841917

申请日：1977-10-13

Applicant: Howard L. Parks ,  John M. Kuronen

Inventor： Howard L. Parks ,  John M. Kuronen

IPC: H05K1/00 ,  H05K3/28 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K1/12 ,  H05K3/36

CPC classification number: H01R12/62 ,  H05K3/4007 ,  H05K1/0393 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09336 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/1572 ,  H05K3/281 ,  H05K3/423 ,  H05K3/4647 ,  Y10T29/49126

Abstract: A flexible connector cable for providing high density and reliable electrical interconnections between printed circuit boards or any other surfaces having conductive paths that need connection to conductive paths on adjacent surfaces. The connector cable comprises a flat flexible laminar structure including an electrically-insulative layer and an electrically-conductive layer. The insulative layer is typically formed on a bonded plastic such as Polyimide and the conductive layer is typically formed of copper. Openings are formed in the insulative layer to expose the conductive layer and raised contacts or buttons are deposited on the conductive layer on both surfaces of the cable. The raised contacts are formed of ductile conductive material which exhibits plastic deformation under pressure to form good electrical connections.

Abstract translation: 一种柔性连接器电缆，用于在印刷电路板或具有需要连接到相邻表面上的导电路径的导电路径的任何其它表面之间提供高密度和可靠的电互连。 连接器电缆包括包括电绝缘层和导电层的扁平柔性层状结构。 绝缘层通常形成在诸如聚酰亚胺的粘结塑料上，并且导电层通常由铜形成。 在绝缘层中形成开口以暴露导电层，并且将凸起的触点或按钮沉积在电缆的两个表面上的导电层上。 凸起的触点由韧性导电材料形成，其在压力下表现出塑性变形以形成良好的电连接。

公开(公告)号：US12040305B2

公开(公告)日：2024-07-16

申请号：US18144376

申请日：2023-05-08

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Jong Ok Chun ,  Nozad Karim ,  Richard Chen ,  Giuseppe Selli ,  Michael Kelly

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H05K1/02 ,  H05K7/10 ,  H05K1/11 ,  H05K1/16

CPC classification number: H01L24/49 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/552 ,  H01L23/66 ,  H05K1/0215 ,  H05K7/10 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/115 ,  H05K1/165 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2201/10287 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.

公开(公告)号：US20240107668A1

公开(公告)日：2024-03-28

申请号：US18275930

申请日：2022-02-07

Applicant: LG INNOTEK CO., LTD.

Inventor： Jinhak LEE ,  Daehyeon SEONG ,  Gahui SHIN

IPC: H05K1/11 ,  H01L23/498

CPC classification number: H05K1/113 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/32 ,  H05K2201/094 ,  H05K2201/09481 ,  H05K2201/096

Abstract: A semiconductor package according to an embodiment includes a first insulating layer; a first pad disposed on a first surface of the first insulating layer; a second pad disposed on a second surface of the first insulating layer opposite to the first surface; and a first through part passing through the first insulating layer, wherein the first through part comprises a first-first through electrode disposed in a first region of the first insulating layer; and a first-second through electrode disposed in a second region of the first insulating layer, wherein the second region is adjacent to an outer side surface of the first insulating layer, wherein an outer side surface of the first-second through electrode is positioned on the same plane as the outer side surface of the first insulating layer, and wherein the first pad extends from the first region of the first insulating layer to the second region to connect the first-first through electrode and the first-second through electrode.

公开(公告)号：US20240098896A1

公开(公告)日：2024-03-21

申请号：US18463728

申请日：2023-09-08

Applicant: PanelSemi Corporation

Inventor： Chin-Tang LI ,  Chao-Jung CHEN

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/113 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/0939 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09854

Abstract: An electronic device includes a first substrate, a second substrate, plural conductive pads, plural hole structures, plural connection pads and plural conductive structures. Hole structures penetrate through the first and second substrates, and are arranged corresponding to the conductive pads. Second ends of hole structures are located at the second substrate, and the corresponding conductive pad is exposed by one of the second ends. Connection pads enclose first ends of hole structures. Conductive structures are arranged in the hole structures and electrically connected to corresponding conductive pads and connection pads. The second diameter portion of each conductive structure penetrates through first substrate and conductive pad and is electrically connected to corresponding connection pad and conductive pad, and first diameter portion thereof penetrates through second substrate and is electrically connected to corresponding conductive pad. Each conductive pad defines an opening, which is exposed by second end of corresponding hole structure.

公开(公告)号：US11856702B2

公开(公告)日：2023-12-26

申请号：US17463575

申请日：2021-09-01

Applicant: SHENNAN CIRCUITS CO., LTD.

Inventor： Lixiang Huang ,  Hua Miao

IPC: H05K1/18 ,  H05K1/14

CPC classification number: H05K1/186 ,  H05K1/144 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/1003 ,  H05K2201/10015 ,  H05K2201/10022

Abstract: The present disclosure provides an adapter board, a for manufacturing the same and a circuit board assembly. The adapter board includes a board body, a first component buried in the board body, a first connector located on a first surface of the board body and configured to be connected with a circuit board and a second component, a second connector located on a second surface of the board body and configured to be connected with a second component, a first conductive body and a second conductive body buried in the board body. One end of the first conductive body is connected with the first component. The other end of the first conductive body is connected with the first connector. One end of the second conductive body is connected with the first component. The other end of the second conductive body is connected with the second connector.