公开(公告)号：US20060249833A1

公开(公告)日：2006-11-09

申请号：US11396603

申请日：2006-04-04

Applicant: Toshihiko Ohara ,  Yoshiharu Unami ,  Yuji Inatani ,  Shoji Ito

Inventor： Toshihiko Ohara ,  Yoshiharu Unami ,  Yuji Inatani ,  Shoji Ito

IPC: H01L23/04 ,  H01L21/4763

CPC classification number: H05K3/4617 ,  H05K3/386 ,  H05K3/4046 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2201/10234 ,  H05K2203/0733 ,  H05K2203/1461 ,  Y10T29/49117 ,  Y10T29/49155

Abstract: A method for manufacturing a wiring board comprising an insulating member, comprising: a penetrating hole formation process of forming a penetrating hole in the insulating member; a placement process of inserting a conductive connecting particle into the penetrating hole; a connecting particle pressing process of disposing the conductive layers on both surfaces of the insulating member, pressing the conductive layers toward the connecting particle in the penetrating hole, and deforming the connecting particle in the pressing direction to obtain the connecting member; and a patterning process of patterning the conductive layers, wherein, in the connecting particle pressing process, the pressing is performed such that the cross-sectional area in the direction along the insulating member surface of at least a portion of the connecting member is greater than the contact area of the connecting member with the conductive layers.

Abstract translation: 一种用于制造包括绝缘构件的布线板的方法，包括：在所述绝缘构件中形成贯通孔的贯通孔形成工序; 将导电性连接粒子插入贯通孔的配置工序; 将导电层配置在绝缘部件的两面上的连接粒子挤压工序，将导电层朝向穿透孔内的连接粒子按压，使连接粒子沿按压方向变形，得到连接部件; 以及图案化导电层的图案化工艺，其中在连接粒子压制过程中，进行按压使得沿着连接构件的至少一部分的绝缘构件表面的方向上的横截面积大于 连接构件与导电层的接触面积。

公开(公告)号：US20060244137A1

公开(公告)日：2006-11-02

申请号：US11477111

申请日：2006-06-29

Applicant: Katsumi Kikuchi ,  Tadanori Shimoto ,  Koji Matsui ,  Kazuhiro Baba

Inventor： Katsumi Kikuchi ,  Tadanori Shimoto ,  Koji Matsui ,  Kazuhiro Baba

IPC: H01L23/48

CPC classification number: H01L21/4857 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/20 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/44 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/0376 ,  H05K2203/061 ,  H05K2203/1536 ,  H01L2924/00

Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.

公开(公告)号：US20060237322A1

公开(公告)日：2006-10-26

申请号：US11377142

申请日：2006-03-16

Applicant: Shou-Kuo Hsu

Inventor： Shou-Kuo Hsu

IPC: C25D5/02

CPC classification number: H05K1/0245 ,  H05K1/0237 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969

Abstract: A printed circuit board includes a first ground layer and a second ground layer. The second ground layer is below the first ground layer. A signal transmission line is arranged on the printed circuit board. The first ground layer includes a chamber located below the transmission line. Therefore, the signal transmission line takes the second ground layer as a reference ground layer, so impedance of the signal transmission line is increased.

Abstract translation: 印刷电路板包括第一接地层和第二接地层。 第二接地层位于第一接地层之下。 信号传输线布置在印刷电路板上。 第一接地层包括位于传输线下方的腔室。 因此，信号传输线将第二接地层作为参考接地层，从而信号传输线的阻抗增加。

公开(公告)号：US20060232949A1

公开(公告)日：2006-10-19

申请号：US11404912

申请日：2006-04-17

Applicant: Hideki Osaka

Inventor： Hideki Osaka

IPC: H05K7/06

CPC classification number: H05K1/0236 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/167 ,  H05K2201/044 ,  H05K2201/09681 ,  H05K2201/0969

Abstract: A motherboard for backplane buses is provided that reduces noise due to entry of external signals into signal wiring which interconnects modules, or noise due to any external signals entering a power supply after being routed around the power supply. An EBG pattern formed up of two wiring regions different from each other in impedance is periodically disposed in at least three arrays as part of the power supply layer(s) constituting a microstripline structure (one layer adjacent to a signal layer is a power supply layer, and the other layer-is interposed in air) or a stripline structure (both layers adjacent to a signal layer are power supply layers); the part of the power supply layer(s) not being involved in signal transmission between the modules on the motherboard for backplane buses.

Abstract translation: 提供了用于背板总线的主板，其将由于外部信号进入到互连模块的信号布线而引起的噪声，或者由于任何外部信号在绕过电源而进入电源之后产生的噪声。 由构成微带结构的电源层的一部分（至少与信号层相邻的一层是供电层），在至少三个阵列中周期性地设置由阻抗彼此不同的两个布线区域形成的EBG图案 ，另一层插入空气中）或带状线结构（与信号层相邻的两层是电源层）; 电源层的一部分不涉及用于背板总线的主板上的模块之间的信号传输。

公开(公告)号：US20060226533A1

公开(公告)日：2006-10-12

申请号：US11103048

申请日：2005-04-11

Applicant: Shin-Shing Jiang ,  Sheng-Yuan Lee

Inventor： Shin-Shing Jiang ,  Sheng-Yuan Lee

IPC: H01L23/04

CPC classification number: H01L23/66 ,  H01L23/49827 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09627 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/0979 ,  H01L2924/00

Abstract: The invention discloses a via connection structure with compensative area on a reference plane. The substrate has several conductive layers isolated by the insulation layers. When two conductive lines formed on different conductive layers where a reference plane is sandwiched in, these two conductive lines are not electrical connected because of the insulation layers. Furthermore, a via connection structure is common used to connect these two conductive lines. When a non-conductive area, i.e. the compensative area, on the reference plane is overlapped with a portion of one conductive line and is close to the via connection structure, it compensates the capacitive effect of the via connection structure. By this compensative area and the variety of the via connection structure, the vertical connection between different layers has a well impedance-matched condition and transmits the signal correctly

Abstract translation: 本发明公开了一种在参考平面上具有补偿区域的通孔连接结构。 衬底具有由绝缘层隔离的多个导电层。 当形成在不同导电层上的两个导线被夹在基准面上时，这两条导线由于绝缘层而不是电连接的。 此外，通常使用通孔连接结构来连接这两条导线。 当参考平面上的非导电区域（即，补偿区域）与一条导线的一部分重叠并且靠近通孔连接结构时，它补偿了通孔连接结构的电容效应。 通过该补偿区域和通孔连接结构的种类，不同层之间的垂直连接具有良好的阻抗匹配条件并正确传输信号

公开(公告)号：US07118389B2

公开(公告)日：2006-10-10

申请号：US10871330

申请日：2004-06-18

Applicant: David K. Fork ,  Jurgen Daniel

Inventor： David K. Fork ,  Jurgen Daniel

IPC: H01R12/00

CPC classification number: G01R1/0466 ,  G01R31/2863 ,  H01L24/11 ,  H01L24/81 ,  H01L24/90 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/81052 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81899 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01R12/718 ,  H05K3/326 ,  H05K2201/0367 ,  H05K2201/0969 ,  H05K2201/10734 ,  H01L2924/00015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A socket for solderless connection between a stud-bumped IC chip and a host PCB. The socket includes a three-dimensional (e.g., cylindrical or cubical) hollow metal frame that is either free-standing or supported by an underlying patterned template structure. The metal frame includes side walls that extend away from the host PCB, and a contact structure located at the upper (i.e., free) end of the side walls. The contact structure defines an opening through which a stud bump can be inserted into a central chamber of the metal frame. The side walls and/or the contact structure are formed such that when the tip end of the stud bump is inserted into the central chamber, at least one of the base structure and the sidewall of the stud bump abuts the contact structure at two or more contact points.

Abstract translation: 一个插头，用于在柱形凸起的IC芯片和主机PCB之间进行无焊接连接。 插座包括三维（例如，圆柱形或立方体）中空金属框架，其独立地或由下面的图案化模板结构支撑。 金属框架包括远离主机PCB延伸的侧壁和位于侧壁的上部（即，自由）端的接触结构）。 接触结构限定了一个开口，通过该开口可以将柱形凸块插入到金属框架的中心室中。 侧壁和/或接触结构被形成为使得当柱状凸块的顶端插入到中心室中时，柱形凸块的基部结构和侧壁中的至少一个在两个或更多个位置抵靠接触结构 联络点。

公开(公告)号：US07105911B2

公开(公告)日：2006-09-12

申请号：US10684812

申请日：2003-10-15

Applicant: Koki Ishizaki ,  Takeshi Shirato

Inventor： Koki Ishizaki ,  Takeshi Shirato

IPC: H01L29/00

CPC classification number: H01C17/242 ,  H05K1/092 ,  H05K1/167 ,  H05K3/4644 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/107 ,  H05K2203/171

Abstract: A multilayer electronic substrate is manufactured by employed: a first conductor layer arranged on an insulating substrate; an insulator arranged on the first conductor layer; a resistor arranged on the insulator; and second conductor layers for sandwiching the resistor to be connected to this resistor. In this multilayer electronic substrate, the resistor is trimmed so as to adjust an electric characteristic of a circuit, and a portion of the first conductor layer, which corresponds to a trimming portion of the resistor, is constituted by a first insulating region.

Abstract translation: 通过采用多层电子基板制造：第一导体层，布置在绝缘基板上; 布置在所述第一导体层上的绝缘体; 布置在绝缘体上的电阻器; 以及用于夹持要连接到该电阻器的电阻器的第二导体层。 在该多层电子基板中，对电阻进行修整以调整电路的电特性，并且与电阻器的修整部对应的第一导体层的一部分由第一绝缘区域构成。

公开(公告)号：US20060191715A1

公开(公告)日：2006-08-31

申请号：US11338771

申请日：2006-01-25

Applicant: Masayoshi Koyama ,  Yoshitake Hayashi ,  Kazuo Otani

Inventor： Masayoshi Koyama ,  Yoshitake Hayashi ,  Kazuo Otani

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K3/4614 ,  H05K3/0035 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4652 ,  H05K3/4658 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2203/0278 ,  H05K2203/0554 ,  H05K2203/1453 ,  Y10T29/49165

Abstract: Holes having the same diameter as via holes are formed in predetermined positions in advance when forming wiring patterns on releasable carriers. The carriers with the wiring patterns are bonded on an insulating material, and a laser beam is irradiated from the side of the carrier using the holes in the wiring pattern as a laser mask to form via holes in the insulating material. The via holes and the holes in the carrier are then filled with a conductive paste. With the holes in the carrier that are matched in position with the via holes, lands in the conductor layers are precisely positioned relative to the via holes. A multilayer circuit board thus produced has lower electrical connection resistance and excellent mountability with improved performances. Also a manufacturing method thereof is achieved.

Abstract translation: 当在可拆卸的载体上形成布线图案时，预先形成具有与通孔相同直径的孔。 具有布线图案的载体被接合在绝缘材料上，并且使用布线图案中的孔作为激光掩模从载体的侧面照射激光束，以在绝缘材料中形成通孔。 通孔和载体中的孔然后用导电浆料填充。 通过载体中与通孔的位置匹配的孔，导体层中的焊盘相对于通孔精确定位。 由此制造的多层电路板具有较低的电连接电阻和优异的安装性能，并具有改进的性能。 也可以实现其制造方法。

公开(公告)号：US20060183316A1

公开(公告)日：2006-08-17

申请号：US11397713

申请日：2006-04-05

Applicant: James Larnerd ,  John Lauffer ,  Voya Markovich ,  Kostas Papathomas

Inventor： James Larnerd ,  John Lauffer ,  Voya Markovich ,  Kostas Papathomas

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H05K3/429 ,  H01L2224/13 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/421 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09845

Abstract: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.

Abstract translation: 一种制造印刷电路板的方法，其中导电通孔形成在板结构的两个电介质层内，以便连接指定的导电层。 一个孔连接两个相邻的层，另一个连接两个相邻的层，包括通过另一个孔连接的一个导电层。 也可以使用一个或多个孔连接所有三个导电层。 所得到的孔可以例如用金属电镀或导电或不导电的糊料填充。 在后者的情况下，也可以在浆料上方设置顶部覆盖导电层，例如在板的外表面上用作衬垫等。

公开(公告)号：US20060162958A1

公开(公告)日：2006-07-27

申请号：US11322306

申请日：2006-01-03

Applicant: Tatsuya Miya ,  Kazuharu Kimura

Inventor： Tatsuya Miya ,  Kazuharu Kimura

IPC: H05K1/14

CPC classification number: H05K1/111 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H05K1/0243 ,  H05K3/341 ,  H05K3/3442 ,  H05K2201/0969 ,  H05K2201/10636 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A board for high frequency device includes a plurality of electrode terminals connected to an electronic component or another electronic circuit board by flowable conducting material such as solder, and grooves formed in an electrode terminal of the plurality of electrode terminals and capable of accumulating solder or the like. Specifically, a high frequency component is mounted on the front surface of the high frequency device board, and the plurality of electrode terminals are formed on the rear surface of the high frequency device board. A ground electrode terminal included in the plurality of electrode terminals is formed at the center of the rear surface of the high frequency device board and connected to a ground. The grooves for accumulating solder or the like are formed in the ground electrode terminal. This reduces the possibility of short-circuit between adjacent electrode terminals due to the flowable conducting material such as solder.

Abstract translation: 一种用于高频器件的板包括多个电极端子，其通过诸如焊料的可流动的导电材料连接到电子部件或另一个电子电路板，以及形成在多个电极端子的电极端子中并且能够积聚焊料或 喜欢。 具体地说，在高频器件基板的正面上安装有高频分量，在高频器件基板的背面形成有多个电极端子。 包括在多个电极端子中的接地电极端子形成在高频器件板的后表面的中心并连接到地。 在接地电极端子上形成有用于蓄积焊料等的槽。 这可以减少由于可流动的导电材料如焊料而在相邻电极端子之间短路的可能性。