公开(公告)号：US20130168841A1

公开(公告)日：2013-07-04

申请号：US13340430

申请日：2011-12-29

Applicant: Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

Inventor： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC: H01L23/495 ,  H01L21/326 ,  H05K1/11 ,  B82Y99/00

CPC classification number: H01L23/49827 ,  B82Y10/00 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49822 ,  H01L2224/16225 ,  H05K1/029 ,  H05K3/4038 ,  H05K2201/0248 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/10378 ,  H05K2203/104 ,  H05K2203/105

Abstract: An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.

Abstract translation: 本公开的示例性实现包括具有顶部和底部接口电极和散布在可编程插值器内的导电粒子的可编程插值器。 响应于将能量场施加到可编程内插器，导电颗粒能够在顶部和底部界面电极之间形成对准的构造，以便电连接顶部和底部界面电极。 导电颗粒可具有导电外表面。 此外，导电粒子可以是球形的。 导电颗粒可以在可编程插入器中的界面层中的体积材料内，并且可以固化块状材料以确保顶部和底部界面电极之间的编程路径。

公开(公告)号：US08446736B2

公开(公告)日：2013-05-21

申请号：US12305046

申请日：2008-05-28

Applicant: Takayuki Kita ,  Masaaki Katsumata ,  Tadashi Nakamura ,  Kota Fukasawa ,  Kazuhiro Furugoori

Inventor： Takayuki Kita ,  Masaaki Katsumata ,  Tadashi Nakamura ,  Kota Fukasawa ,  Kazuhiro Furugoori

IPC: H05K1/11

CPC classification number: H05K1/183 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/19105 ,  H05K3/4614 ,  H05K3/4697 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T156/1062 ,  Y10T428/24273 ,  Y10T428/24893 ,  Y10T428/24917 ,  H01L2224/0401

Abstract: An upper board having an opening and forming a circuit on a surface layer, a connection sheet between boards having an opening and forming conductive holes filled with conductive paste in through-holes, and a lower board forming a circuit on a surface layer are stacked up, heated and pressed. In particular, the connection sheet between boards is made of a material different from the upper board and the lower board. A multi-layer circuit board having a cavity structure, and a full-layer IVH structure with high interlayer connection reliability can be manufactured.

Abstract translation: 具有开口并在表面层上形成电路的上板，具有开口的板和在通孔中填充有导电膏的形成导电孔的连接片和在表面层上形成电路的下板被堆叠 ，加热按压。 特别地，板之间的连接片由与上板和下板不同的材料制成。 可以制造具有空腔结构的多层电路板和具有高层间连接可靠性的全层IVH结构。

公开(公告)号：US08378704B2

公开(公告)日：2013-02-19

申请号：US11943105

申请日：2007-11-20

Applicant: Seiichirou Itou ,  Masashi Miyawaki ,  Takeshi Oyamada

Inventor： Seiichirou Itou ,  Masashi Miyawaki ,  Takeshi Oyamada

IPC: G01R31/00

CPC classification number: G01R3/00 ,  G01R1/07378 ,  H05K3/386 ,  H05K3/4614 ,  H05K3/4623 ,  H05K3/4626 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/1476 ,  Y10T29/49126

Abstract: A substrate is provided for a probe card assembly. The substrate includes an interconnection layer including a first surface having a first electrode set and a second surface having a second electrode set electrically connected to the first electrode set. The substrate further includes a base layer including a first surface having a third electrode set electrically connected to the second electrode set and a second surface having a plurality of contact terminals electrically connected to the third electrode set. And the substrate further includes a resin layer including a plurality of sublayers made of different materials. The resin layer is attached to the first surface of the base layer and the second surface of the interconnection layer.

Abstract translation: 为探针卡组件提供基板。 衬底包括互连层，其包括具有第一电极组的第一表面和具有电连接到第一电极组的第二电极组的第二表面。 所述基板还包括基底层，所述基底层包括具有电连接到所述第二电极组的第三电极组的第一表面和具有电连接到所述第三电极组的多个接触端子的第二表面。 并且所述基板还包括包括由不同材料制成的多个子层的树脂层。 树脂层附接到基底层的第一表面和互连层的第二表面。

公开(公告)号：US08371026B2

公开(公告)日：2013-02-12

申请号：US12267705

申请日：2008-11-10

Applicant: Masato Nomiya ,  Norio Sakai ,  Mitsuyoshi Nishide

Inventor： Masato Nomiya ,  Norio Sakai ,  Mitsuyoshi Nishide

IPC: H05K3/30 ,  H05K1/03

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K3/305 ,  H05K3/4626 ,  H05K3/4629 ,  H05K2201/0116 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1147 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: In a method for manufacturing a multilayer ceramic electronic device, a multilayer ceramic element assembly is prepared that includes laminated unsintered ceramic base material layers, a first conductor pattern, a seat portion disposed in a surface of the multilayer ceramic element assembly and arranged to mount a surface mount electronic device thereon, a second conductor pattern connected to the surface mount electronic device, and a resin introduction portion located outside a vertically projected region of the surface mount electronic device and arranged to introduce a resin to the seat portion. The multilayer ceramic element assembly is fired and the surface mount electronic device is mounted on the seat portion of the fired multilayer ceramic element assembly with the second conductor pattern therebetween. The resin is filled from the resin introduction portion into the seat portion and between the seat portion and the surface mount electronic device, and the resin is cured.

Abstract translation: 在制造多层陶瓷电子器件的方法中，制备多层陶瓷元件组件，其包括层叠的未烧结陶瓷基材层，第一导体图案，设置在多层陶瓷元件组件的表面中的座部， 表面安装电子器件，连接到表面安装电子器件的第二导体图案，以及位于表面安装电子器件的垂直投影区域外侧的树脂引入部，并且布置成将树脂引入座部。 烧结多层陶瓷元件组件，并且表面安装电子器件安装在烧制的多层陶瓷元件组件的座部上，其间具有第二导体图案。 树脂从树脂引入部分填充到座椅部分中，并且在座椅部分和表面安装电子设备之间，并且树脂被固化。

公开(公告)号：US08367942B2

公开(公告)日：2013-02-05

申请号：US12589719

申请日：2009-10-27

Applicant: David Gregory Howell ,  Hao-Yun Ma

Inventor： David Gregory Howell ,  Hao-Yun Ma

IPC: H05K1/11

CPC classification number: H01R43/007 ,  D03D1/0088 ,  D03D15/00 ,  D10B2401/16 ,  H01R12/714 ,  H01R13/6467 ,  H05K3/325 ,  H05K7/1053 ,  H05K2201/0133 ,  H05K2201/029 ,  H05K2201/10378 ,  Y10T29/49217 ,  Y10T442/2418 ,  Y10T442/2475

Abstract: An electrical interposer for connecting two electronic devices includes a plurality of first cores with undulating structure extending in a first direction and a plurality of second cores with undulating structure extending in a second direction angular with the first direction. Each first core has first peaks and first valleys alternately arranged in the first direction and each first peak is electrically connected with a corresponding neighboring first valley but insulated from others. Each second core has second peaks and second valleys alternately arranged in the second direction and each second peak is electrically connected with a corresponding neighboring second valley but insulated from others. The first cores and the second cores interlace with each other to reach a woven structure with the first peaks and the second peaks jointly constituting an upper interface, and the first valleys and the second valleys jointly constituting a lower interface.

Abstract translation: 用于连接两个电子设备的电插入器包括具有在第一方向上延伸的起伏结构的多个第一芯和具有沿与第一方向成角度的第二方向延伸的起伏结构的多个第二芯。 每个第一芯具有沿第一方向交替布置的第一峰和第一谷，并且每个第一峰与相应的相邻的第一谷电连接，但是与其他顶部绝缘。 每个第二芯具有沿第二方向交替布置的第二峰和第二谷，并且每个第二峰与相应的相邻的第二谷电连接，但与其绝缘。 第一芯和第二芯彼此交织以达到编织结构，其中第一峰和第二峰共同构成上界面，第一谷和第二谷共同构成下界面。

公开(公告)号：US20130026509A1

公开(公告)日：2013-01-31

申请号：US13640869

申请日：2011-04-14

Applicant: Naoya Tohyama ,  Takuya Inoue ,  Koichi Kumagai ,  Takaha Kunieda

Inventor： Naoya Tohyama ,  Takuya Inoue ,  Koichi Kumagai ,  Takaha Kunieda

IPC: H01L33/08 ,  H01L33/64 ,  H01L33/62

CPC classification number: H01L25/167 ,  F21K9/23 ,  F21V3/00 ,  F21Y2115/10 ,  H01L33/648 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/3025 ,  H05K1/0201 ,  H05K1/0203 ,  H05K1/0306 ,  H05K1/144 ,  H05K3/0061 ,  H05K2201/062 ,  H05K2201/10106 ,  H05K2201/10378 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention includes one or more LED elements, a silicon substrate on which the LED elements are mounted via micro bumps and internally formed wiring is connected to the micro bumps, a heat insulation organic substrate which is stuck to the opposite side of the LED elements-mounting side of the silicon substrate and has through-holes in which the wiring goes through, a chip-mounting substrate which is stuck to the opposite side of the silicon substrate side of the heat insulation organic substrate and internally formed wiring is connected to wiring in the through-holes of the heat insulation organic substrate, and an LED control circuit chip which is connected to the wiring of the chip-mounting substrate via micro bumps, and mounted via the micro bumps on the opposite side of the heat insulation organic substrate side of the chip-mounting substrate.

Abstract translation: 本发明包括一个或多个LED元件，通过微型凸块安装LED元件的硅衬底，并且内部形成的布线连接到微型突起，与LED元件的相对侧粘贴的隔热有机衬底， 硅基板的安装侧，并且具有布线穿过的通孔，粘贴在隔热有机基板的硅基板侧的相反侧的芯片安装基板和内部形成的布线连接到布线 隔热有机基板的通孔，以及通过微型突起与芯片安装基板的布线连接的LED控制电路芯片，并且经由隔热有机基板侧的相反侧的微凸块安装 的芯片安装基板。

公开(公告)号：US08363418B2

公开(公告)日：2013-01-29

申请号：US13163502

申请日：2011-06-17

Applicant: Morgan Johnson ,  Frederick G. Weiss

Inventor： Morgan Johnson ,  Frederick G. Weiss

IPC: H05K7/00

CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.

Abstract translation: 插入器衬底包括插入器衬底中的互连阵列，所述连接器阵列根据用于电路衬底上的处理器的互连阵列布置，所述插入器衬底中的至少一个导电迹线与至少一个连接器 所述互连阵列，所述导电迹线平行于所述插入器基板布置，使得在所述插入器基板中的所述连接器与所述电路基板上的所述处理器的相应的一个互连件之间不存在电连接;以及至少一个外围电路， 所述插入器衬底与所述导电迹线电连接。

公开(公告)号：US20130003314A1

公开(公告)日：2013-01-03

申请号：US13578791

申请日：2011-02-21

Applicant: Yusuke Igarashi ,  Takeshi Nakamura

Inventor： Yusuke Igarashi ,  Takeshi Nakamura

IPC: H05K1/03 ,  H05K3/10 ,  H05K7/06

CPC classification number: H05K3/4608 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19105 ,  H05K1/185 ,  H05K2201/10378 ,  H05K2203/063 ,  H05K2203/1469 ,  Y10T29/49162 ,  H01L2924/00

Abstract: Provided is a substrate wherein wiring layers laminated onto the top and bottom surfaces of a core layer are connected to each other by a simple means. Also provided is a method for manufacturing said substrate. In the provided substrate (10A), a connection substrate (13) is placed in a removed region (12) which goes all the way through a part of a thick core layer (11). Said connection substrate (13) electrically connects a first wiring layer (16A) laminated onto the top surface of the core layer (11) to a second wiring layer (16B) laminated onto the bottom surface of the core layer (11). This eliminates the requirement of providing a through-hole through the core layer (11) for each connection, resulting in a small form-factor substrate (10A) with a high wiring density.

Abstract translation: 提供了一种基板，其中层叠在芯层的顶表面和底表面上的布线层通过简单的方式彼此连接。 还提供了制造所述基板的方法。 在所提供的基板（10A）中，将连接基板（13）放置在穿过厚芯层（11）的一部分的去除区域（12）中。 所述连接基板（13）将层叠在芯层（11）的上表面上的第一布线层（16A）与叠层在芯层（11）的底面上的第二布线层（16B）电连接。 这消除了对于每个连接通过芯层（11）提供通孔的要求，导致具有高布线密度的小形状因子衬底（10A）。

公开(公告)号：US08344264B2

公开(公告)日：2013-01-01

申请号：US12489818

申请日：2009-06-23

Applicant: Yutaka Kumano ,  Hideki Iwaki ,  Tetsuyoshi Ogura ,  Shingo Komatsu ,  Koichi Hirano

Inventor： Yutaka Kumano ,  Hideki Iwaki ,  Tetsuyoshi Ogura ,  Shingo Komatsu ,  Koichi Hirano

IPC: H05K1/11

CPC classification number: H05K3/4046 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K3/4647 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2201/10416 ,  H05K2203/0152 ,  Y10T29/49162 ,  H01L2924/00

Abstract: A pair of discretionary points on a principal surface of a block are coupled to each other with a metal wire having a length larger than a distance between the pair of discretionary points, liquid resin is applied to the principal surface so as to cover the metal wire and then cured, so that a resin-cured material is formed, and the upper-surface portion of the resin-cured material is removed together with an intermediate portion of the metal wire, and then the block is removed from the resin-cured material.

Abstract translation: 块的主表面上的一对自由点通过长度大于所述一对自由点之间的距离的金属线彼此连接，液体树脂施加到主表面以覆盖金属线 然后固化，从而形成树脂固化材料，树脂固化材料的上表面部分与金属丝的中间部分一起除去，然后将该块从树脂固化材料上除去 。

公开(公告)号：US20120305303A1

公开(公告)日：2012-12-06

申请号：US13153608

申请日：2011-06-06

Applicant: Md Altaf Hossain ,  Cliff C. Lee ,  David W. Browning ,  Itai M. Pines ,  Brian P. Kelly

Inventor： Md Altaf Hossain ,  Cliff C. Lee ,  David W. Browning ,  Itai M. Pines ,  Brian P. Kelly

IPC: H05K1/16 ,  H05K1/11 ,  H05K1/00

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/12042 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09972 ,  H05K2201/10378 ,  H01L2924/014 ,  H01L2924/00

Abstract: The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.

Abstract translation: 本公开涉及被制造为具有重叠的连接区域的微电子衬底，例如插入件，母板，测试平台等，使得不同的微电子器件，例如微处理器，芯片组，图形处理器件，无线器件，存储器 设备，专用集成电路等可以交替地附接到微电子基板以形成功能微电子封装。