公开(公告)号：US20110080715A1

公开(公告)日：2011-04-07

申请号：US12574777

申请日：2009-10-07

Applicant: Lin Chiao-Li

Inventor： Lin Chiao-Li

IPC: H05K1/14 ,  G06F21/00

CPC classification number: H05K1/141 ,  G06F21/86 ,  G06F2221/2143 ,  H05K1/0275 ,  H05K1/182 ,  H05K2201/09036 ,  H05K2201/10477 ,  H05K2201/10689

Abstract: The present invention discloses a protective structure of an electronic component comprises a first circuit board, a second circuit board, and a chip module. The first circuit board is provided thereon with a hollow accommodating space and a plurality of first electrode contacts. The second circuit board is provided thereon with a plurality of second electrode contacts. The chip module is disposed in an area enclosed by the second electrode contacts. The hollow accommodating space is topped with the second circuit board such that the chip module is encapsulated between the second circuit board and the hollow accommodating space. Upon detection of separation of the first and second circuit boards under an external force or detection of a short circuit caused to an electrical circuit inside the first circuit board or the second circuit board, the chip module activates a security protection mechanism for deleting information stored thereon so as to prevent the information from being abused.

Abstract translation: 本发明公开了一种电子部件的保护结构，包括第一电路板，第二电路板和芯片模块。 第一电路板设置有中空容纳空间和多个第一电极触点。 第二电路板设置有多个第二电极触点。 芯片模块设置在由第二电极触点包围的区域中。 中空容纳空间与第二电路板顶起，使得芯片模块封装在第二电路板和中空容纳空间之间。 在检测到第一和第二电路板在外力下分离或检测到由第一电路板或第二电路板内的电路引起的短路时，芯片模块激活用于删除存储在其上的信息的安全保护机制 以防止信息被滥用。

公开(公告)号：US20110026887A1

公开(公告)日：2011-02-03

申请号：US12726479

申请日：2010-03-18

Applicant: Hiroshi Uemura ,  Hideto Furuyama

Inventor： Hiroshi Uemura ,  Hideto Furuyama

IPC: G02B6/43

CPC classification number: H05K1/0203 ,  H05K1/147 ,  H05K2201/10121 ,  H05K2201/10477

Abstract: In a mounting structure formed by mounting an optoelectronic interconnection module on a mounting board, an optical semiconductor device, electrical wires and electrical connection terminals are provided on the main surface of an optoelectronic interconnection board having flexibility on the optoelectronic interconnection module and an optical interconnection path is provided at the optoelectronic interconnection board. Electrical wires and electrical connection terminals are provided on the main surface of the mounting board. A conductive connection member is disposed between the electrical connection terminals on the optoelectronic interconnection module side and the electrical connection terminals on the mounting board side. A heat release member that releases heat of the optical semiconductor device to the mounting board side is disposed between the optical semiconductor device and the mounting board.

Abstract translation: 在通过将光电互连模块安装在安装板上形成的安装结构中，光学半导体器件，电线和电连接端子设置在光电互连板的主表面上，该光电互连板在光电互连模块上具有柔性，并且光学互连路径 设在光电互连板上。 电线和电气连接端子设置在安装板的主表面上。 导电连接构件设置在光电互连模块侧的电连接端子与安装板侧的电连接端子之间。 在光半导体装置和安装基板之间配置有将光半导体装置向安装基板侧的散热的散热构件。

公开(公告)号：US07851708B2

公开(公告)日：2010-12-14

申请号：US12186546

申请日：2008-08-06

Applicant: Norio Sakai ,  Mitsuyoshi Nishide

Inventor： Norio Sakai ,  Mitsuyoshi Nishide

IPC: H05K1/03

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/4611 ,  H05K2201/10378 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2201/2018 ,  H05K2203/1572 ,  Y10T29/49121 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a composite body, a frame body includes a frame member and a plurality of connection members formed by bending thin metal plates. The frame member includes a through-hole and extends along a peripheral portion of a substrate body. Each of the plurality of connection members has a first strip and a second strip continuously connected to opposed ends of a middle strip. The connection members are disposed in the frame member. Each of the first and second strips of the connection member is exposed on a major surface extending around the through-hole. The first strip and the second strip extend in a direction in which the connection members face each other, and opposed ends of the middle strip are continuously connected to the first strip and the second strip on the side adjacent to the through-hole. The middle strip extends through the inside of the frame member.

Abstract translation: 在复合体中，框体包括框架构件和通过弯曲薄金属板形成的多个连接构件。 框架构件包括通孔并且沿着基板主体的周边部分延伸。 多个连接构件中的每一个具有连续地连接到中间带的相对端的第一条带和第二条带。 连接构件设置在框架构件中。 连接构件的第一和第二条带中的每一个暴露在围绕通孔延伸的主表面上。 第一条带和第二条带在连接部件彼此面对的方向上延伸，并且中间条带的相对端部与邻近通孔的一侧连续地连接到第一条带和第二条带。 中间条延伸穿过框架构件的内部。

公开(公告)号：US07729121B1

公开(公告)日：2010-06-01

申请号：US12317855

申请日：2008-12-30

Applicant: Anand Deshpande ,  Venkat Natarajan ,  Ashok Kabadi ,  Vittal Kini

Inventor： Anand Deshpande ,  Venkat Natarajan ,  Ashok Kabadi ,  Vittal Kini

IPC: H05K7/20

CPC classification number: H01L23/3677 ,  H01L23/40 ,  H01L23/427 ,  H01L2224/73253 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/325 ,  H05K2201/10159 ,  H05K2201/10325 ,  H05K2201/10477 ,  H05K2201/10719

Abstract: In some embodiments, a stacked package assembly may include a first socket defining an interior cavity, a first semiconductor device coupled to the first socket, a second socket positioned within the interior cavity of the first socket, and a second semiconductor device removably coupled to the second socket within the cavity of the first socket. The second socket may be positioned between the first semiconductor device and the second semiconductor device and provide an electrical connection between the first semiconductor device and the second semiconductor device. Other embodiments are disclosed and claimed.

Abstract translation: 在一些实施例中，堆叠的包装组件可以包括限定内部空腔的第一插座，耦合到第一插座的第一半导体器件，位于第一插座的内部空腔内的第二插座，以及可移除地耦合到 在第一插座的腔内的第二插座。 第二插座可以位于第一半导体器件和第二半导体器件之间，并且在第一半导体器件和第二半导体器件之间提供电连接。 公开和要求保护其他实施例。

公开(公告)号：US07604153B2

公开(公告)日：2009-10-20

申请号：US11370500

申请日：2006-03-07

Applicant: John MacKay ,  Tom Molinaro

Inventor： John MacKay ,  Tom Molinaro

IPC: B23K31/02 ,  H01L21/44

CPC classification number: B23K35/22 ,  B23K1/0016 ,  B23K3/0623 ,  B23K3/0638 ,  B23K3/087 ,  B23K35/0222 ,  B23K35/0244 ,  B23K35/224 ,  B23K2101/40 ,  B23K2101/42 ,  H01L21/4853 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13011 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16 ,  H01L2224/1613 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K3/3484 ,  H05K2201/10477 ,  H05K2203/0113 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/043 ,  H05K2203/0557 ,  H05K2203/085 ,  H05K2203/1581 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A mask (stencil) having cells (openings) is disposed on a surface of a heater stage, and is then filled (printed) with solder paste. Then a substrate is assembled to the opposite side of the mask. Then the solder paste is reflowed. This may be done partially inverted. Then the mask is separated from the substrate, either before or after cooling. Solder balls are thus formed on the substrate, which may be a semiconductor wafer. A biased chuck urges the substrate into intimate contact with the mask. A method for printing the mask with solder paste is described. Methods of forming high aspect ratio solder bumps (including balls and reflowable interconnect structures) are described.

Abstract translation: 具有电池（开口）的面罩（模板）设置在加热器台的表面上，然后用焊膏填充（印刷）。 然后将基板组装到掩模的相对侧。 然后焊膏被回流。 这可能会部分颠倒。 然后在冷却之前或之后将掩模与基底分离。 因此，焊盘形成在衬底上，该衬底可以是半导体晶片。 偏置的卡盘促使基底与掩模紧密接触。 描述了用焊膏印刷掩模的方法。 描述形成高纵横比焊料凸块（包括球和可回流互连结构）的方法。

公开(公告)号：US20090159331A1

公开(公告)日：2009-06-25

申请号：US12297022

申请日：2007-04-11

Applicant: Johannes W. Weekamp ,  Cornelis Slob ,  Jacob M. Scheer ,  Freerk E. Van Straten

Inventor： Johannes W. Weekamp ,  Cornelis Slob ,  Jacob M. Scheer ,  Freerk E. Van Straten

IPC: H05K7/02 ,  H05K1/11 ,  B23K1/00 ,  B23K37/00

CPC classification number: B81C1/00833 ,  B81C1/00269 ,  B81C2203/035 ,  H05K3/341 ,  H05K2201/10371 ,  H05K2201/10477 ,  H05K2203/1147 ,  Y02P70/613 ,  Y10T29/49117

Abstract: The present invention relates to a method for manufacturing an electronic assembly (50) comprising an electronic component, a cavity and a substrate which method comprises; —providing an electronic component (10) having a first pattern with a substantially closed configuration; —providing a cover (18) on a surface of the electronic component, which cover together with said surface defines a cavity (20), the closed configuration of the first pattern substantially enclosing the cover at said surface; —providing a substrate (30) having a second pattern with a substantially closed configuration, which closed configuration at least partially corresponds to the closed configuration of the first pattern and comprises a solder pad; —disposing solder material at the solder pad; —positioning the electronic component and the substrate so as to align both the substantially closed configurations of the first and second pattern, while the substrate supports a top surface (28) of the cover; —reflow-soldering the solder material, therewith providing a soldered connection (52) between the first and second pattern. Furthermore the present invention relates to an electronic assembly (50), a cover (18) and a substrate (30).

Abstract translation: 本发明涉及一种用于制造电子组件（50）的方法，所述电子组件（50）包括电子部件，空腔和基板，所述方法包括： - 提供具有基本上封闭构造的第一图案的电子部件（10） - 提供与所述表面一起覆盖的所述电子部件的表面上的盖子（18）限定空腔（20），所述第一图案的所述封闭构造基本上在所述表面上包围所述盖子; - 提供具有基本封闭构造的第二图案的衬底（30），该封闭构造至少部分对应于第一图案的封闭构造，并且包括焊盘; - 在焊料垫上涂抹焊料; - 定位所述电子部件和所述基板，以使所述第一和第二图案的所述基本上封闭的构造对准，同时所述基板支撑所述盖的顶表面（28）; - 回流焊接焊料材料，从而在第一和第二图案之间提供焊接连接（52）。 此外，本发明涉及电子组件（50），盖（18）和基板（30）。

公开(公告)号：US07482678B2

公开(公告)日：2009-01-27

申请号：US10539735

申请日：2003-12-08

Applicant: Philippe Kertesz ,  Bernard Ledain ,  Daniel Caban-Chastas

Inventor： Philippe Kertesz ,  Bernard Ledain ,  Daniel Caban-Chastas

IPC: H01L23/552 ,  H01L23/48

CPC classification number: H05K1/0243 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6622 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K3/3436 ,  H05K2201/10371 ,  H05K2201/10477 ,  H05K2201/10727 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a microwave package delimiting an interior volume, comprising a Faraday cage formed by a conducting surface surrounding the interior volume, a connection point placed outside the Faraday cage, the connection point being intended to be linked electrically to an exterior circuit, an input-output passing through the Faraday cage and linked electrically to the connection point, a base forming a face of the package, the exterior surface of the base forming a mounting surface intended to be applied to the exterior circuit, the connection point being placed on the mounting surface, so that the connection point is placed between the Faraday cage and the exterior circuit when the package is mounted on the exterior circuit. The invention applies to microwave packages used in the realms of avionics, telecommunications, space.

Abstract translation: 本发明涉及一种限定内部容积的微波包装，包括由围绕内部容积的导电表面形成的法拉第笼，设在法拉第笼外部的连接点，该连接点旨在与外部电路电连接， 输入输出通过法拉第笼并且与连接点电连接，形成封装的表面的基座，基座的外表面形成用于施加到外部电路的安装表面，连接点被放置在 安装表面，使得当包装安装在外部电路上时，连接点位于法拉第笼和外部电路之间。 本发明适用于航空电子，电信，空间领域中使用的微波封装。

公开(公告)号：US20090002973A1

公开(公告)日：2009-01-01

申请号：US12093496

申请日：2006-11-08

Applicant: Shinji Watanabe ,  Nobuhiro Mikami ,  Junya Sato ,  Kenichiro Fujii ,  Katsumi Abe ,  Atsumasa Sawada

Inventor： Shinji Watanabe ,  Nobuhiro Mikami ,  Junya Sato ,  Kenichiro Fujii ,  Katsumi Abe ,  Atsumasa Sawada

IPC: H05K7/00

CPC classification number: H05K1/18 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1515 ,  H01L2924/15151 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/023 ,  H05K1/0271 ,  H05K1/0284 ,  H05K1/185 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/32 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09436 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2203/1469 ,  H05K2203/302 ,  Y02P70/611 ,  H01L2924/00

Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.

Abstract translation: 本发明的目的在于，当将半导体封装安装在弯曲的基板上时，可以抑制对半导体封装件施加的应力。 在安装基板1中，将半导体封装20安装在其至少一部分上包括弯曲表面的弯曲板10上。 弯曲板10包括设置在半导体封装20安装的弯曲表面部分的区域上并具有平坦的上表面的基座部分13a和设置在基座部分的平坦表面上的多个焊盘部分15a 13a。 基座部分13a由绝缘材料形成。 半导体封装20安装在焊盘部分15a上。

公开(公告)号：US20080289853A1

公开(公告)日：2008-11-27

申请号：US12186546

申请日：2008-08-06

Applicant: Norio SAKAI ,  Mitsuyoshi NISHIDE

Inventor： Norio SAKAI ,  Mitsuyoshi NISHIDE

IPC: H01R43/00 ,  H01B5/00

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/4611 ,  H05K2201/10378 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2201/2018 ,  H05K2203/1572 ,  Y10T29/49121 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a composite body, a frame body to be connected to a first major surface of a substrate body includes a frame member made of an insulating material and a plurality of connection members formed by bending thin metal plates. The frame member includes a through-hole at the approximate center thereof and extends along a peripheral portion of the first major surface of the substrate body so as to define a frame shape. Each of the plurality of connection members has a first strip and a second strip continuously connected to opposed ends of a middle strip. The connection members are disposed in the frame member so as to face each other with the through-hole therebetween. Each of the first strip and the second strip of the connection member is exposed on a corresponding one of the two major surfaces extending around the through-hole of the frame member. The first strip and the second strip extend in a direction in which the connection members face each other with the through-hole therebetween, and the opposed ends of the middle strip are continuously connected to an end of the first strip and an end of the second strip on the side adjacent to the through-hole. The middle strip extends through the inside of the frame member.

Abstract translation: 在复合体中，要连接到基体的第一主表面的框体包括由绝缘材料制成的框架构件和通过弯曲薄金属板形成的多个连接构件。 框架构件在其大致中心处包括通孔，并且沿着基板主体的第一主表面的周边部分延伸以限定框架形状。 多个连接构件中的每一个具有连续地连接到中间带的相对端部的第一条带和第二条带。 连接构件通过其间的通孔设置在框架构件中以彼此面对。 连接构件的第一条带和第二条带中的每一个暴露在围绕框架构件的通孔延伸的两个主表面中的对应的一个表面上。 第一条带和第二条带沿着连接部件彼此面对的方向延伸，并且中间条带的相对端部连续地连接到第一条带的端部，并且第二条带的端部 在与通孔相邻的一侧的条带。 中间条延伸穿过框架构件的内部。

公开(公告)号：US20080272829A1

公开(公告)日：2008-11-06

申请号：US11839606

申请日：2007-08-16

Applicant: Takehiko Maeda

Inventor： Takehiko Maeda

IPC: G05F1/00

CPC classification number: H01L25/16 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/181 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09481 ,  H05K2201/10477 ,  H05K2201/1053 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment of the present invention, a semiconductor device includes a multilayer wiring board, a DC power supply circuit and a semiconductor integrated circuit chip. The multilayer wiring board has the semiconductor integrated circuit chip embedded therein. The DC power supply circuit is provided on the multilayer wiring board. The DC power supply circuit receives a power supply and converts a voltage of the power supply into a plurality of voltages having different levels from one another. The DC power supply circuit supplies a power supply voltage to the semiconductor integrated circuit chip.

Abstract translation: 在本发明的一个实施例中，半导体器件包括多层布线板，直流电源电路和半导体集成电路芯片。 多层布线基板上嵌有半导体集成电路芯片。 直流电源电路设置在多层布线板上。 直流电源电路接收电源，并将电源的电压转换成具有彼此不同电平的多个电压。 直流电源电路向半导体集成电路芯片供给电源电压。