公开(公告)号：US20080236878A1

公开(公告)日：2008-10-02

申请号：US12076989

申请日：2008-03-26

Applicant: Seung Eun Lee ,  Yul Kyo Chung ,  Jung Won Lee ,  In Hyung Lee ,  Byung Ik Song

Inventor： Seung Eun Lee ,  Yul Kyo Chung ,  Jung Won Lee ,  In Hyung Lee ,  Byung Ik Song

IPC: H05K1/18 ,  H01G4/10 ,  H01G7/00

CPC classification number: H05K1/162 ,  H01G4/105 ,  H01G4/33 ,  H05K2201/0175 ,  H05K2201/0179 ,  Y10T29/435

Abstract: There is provided a thin film capacitor and a capacitor-embedded printed board improved in leakage current characteristics. A dielectric layer is formed of a BiZnNb-based amorphous metal oxide with a predetermined dielectric constant without being heat treated at a high temperature, and metallic phase bismuth of the BiZnNb-based amorphous metal oxide is adjusted in content to attain a desired dielectric constant. Also, another dielectric layer having a different content of metallic phase bismuth may be formed. The thin film capacitor including: a first electrode; a dielectric layer including a first dielectric film formed on the first electrode, the dielectric layer comprising a BiZnNb-based amorphous metal oxide; and a second electrode formed on the dielectric layer, wherein the BiZnNb-based amorphous metal oxide contains metallic phase bismuth.

Abstract translation: 提供了薄膜电容器和电容器嵌入式印刷电路板，改善了漏电流特性。 电介质层由具有预定介电常数的BiZnNb基非晶态金属氧化物形成，而不在高温下进行热处理，并且将BiZnNb基非晶态金属氧化物的金属相铋的含量调节到所需的介电常数。 此外，可以形成具有不同金属相铋含量的另一介质层。 所述薄膜电容器包括：第一电极; 介电层，包括形成在所述第一电极上的第一电介质膜，所述电介质层包含BiZnNb基非晶态金属氧化物; 以及形成在所述电介质层上的第二电极，其中所述BiZnNb基非晶态金属氧化物含有金属相铋。

公开(公告)号：US20080190656A1

公开(公告)日：2008-08-14

申请号：US11579727

申请日：2005-05-06

Applicant: David Cheeke ,  Leslie M. Landsberger

Inventor： David Cheeke ,  Leslie M. Landsberger

IPC: H05K1/02 ,  H05K3/30

CPC classification number: H05K1/167 ,  H05K1/0212 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/062 ,  H05K2203/171 ,  Y10T29/49155

Abstract: There is described a printed circuit board with a thermally trimmable component embedded therein. A layer of refractory insulating material is provided to provide mechanical support and chemical passivation for the thermally trimmable component. The component is trimmed by applying a sequence of heat pulses the a heating element, which could be the component itself or a separate element. A cavity may be burned in the substrate to provide thermal isolation for the thermally trimmable component.

Abstract translation: 描述了嵌入其中的可热调制组件的印刷电路板。 提供一层难熔绝缘材料，为热可调节部件提供机械支撑和化学钝化。 通过施加加热元件的加热元件序列来修剪部件，加热元件可以是部件本身或单独的元件。 空腔可以在基板中燃烧以提供热可分离组件的热隔离。

公开(公告)号：US20080106844A1

公开(公告)日：2008-05-08

申请号：US11972579

申请日：2008-01-10

Applicant: Cengiz Palanduz ,  Dustin Wood

Inventor： Cengiz Palanduz ,  Dustin Wood

IPC: H01G4/012 ,  H05K7/02

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/20 ,  H01G4/33 ,  H01L2224/16225 ,  H05K1/0306 ,  H05K1/097 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10545 ,  Y10T29/435

Abstract: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.

Abstract translation: 一种方法，包括将包含一定量的陶瓷材料的纳米颗粒的胶体悬浮液沉积在基底上; 并对悬浮液进行热处理以形成薄膜。 一种方法，包括将陶瓷材料的多个纳米颗粒沉积在衬底的表面上的预定位置; 并对多个纳米颗粒进行热处理以形成薄膜。 一种包括计算设备的系统，包括微处理器，所述微处理器通过衬底耦合到印刷电路板，所述衬底包括形成在表面上的至少一个电容器结构，所述电容器结构包括第一电极，第二电极和陶瓷 设置在第一电极和第二电极之间的材料，其中陶瓷材料包括柱状晶粒。

公开(公告)号：US20080104833A1

公开(公告)日：2008-05-08

申请号：US11964355

申请日：2007-12-26

Applicant: Takashi KARIYA ,  Akira MOCHIDA

Inventor： Takashi KARIYA ,  Akira MOCHIDA

IPC: H05K3/30 ,  H01K3/10 ,  H05K3/10 ,  H05K1/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2203/0353 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: In a printed wiring board 10, an upper electrode connecting portion 52 penetrates through a capacitor portion 40 in top to bottom direction so that an upper electrode connecting portion first part 52a is not in contact with the capacitor portion 40, passes through an upper electrode connecting portion third part 52c provided at the upper portion of the capacitor portion 40, and then connects from the upper electrode connecting portion second part 52b to an upper electrode 42. Furthermore, a lower electrode connecting portion 51 penetrates through the capacitor portion 40 in top to bottom direction so that it is not in contact with the upper electrode 42 of the capacitor portion 40, but is in contact with a lower electrode 41. Therefore, the upper electrode connecting portion 52 and the lower electrode connecting portion 51 can be formed even after in process of build-up, the whole surface is covered by a high dielectric capacitor sheet that has a structure that a high dielectric layer is sandwiched between two metal foils and will afterwards serve as the capacitor portion 40.

Abstract translation: 在印刷布线板10中，上部电极连接部52从上下方向贯穿电容器部40，使上部电极连接部第一部分52a不与电容器部40接触，通过上部电极 连接部分第三部分52c设置在电容器部分40的上部，然后从上电极连接部分第二部分52b连接到上电极42。 此外，下电极连接部51从上下方向贯通电容器部40，使其不与电容器部40的上部电极42接触，而与下部电极41接触。 因此，上部电极连接部52和下部电极连接部51即使在积聚的过程中也可以形成，整个表面被高介电电容器片覆盖，该介电电容片具有将介电层夹在高介电层之间的结构 两个金属箔，然后用作电容器部分40。

公开(公告)号：US20080096310A1

公开(公告)日：2008-04-24

申请号：US11541233

申请日：2006-09-29

Applicant: Mitul Modi ,  Sudarshan V. Rangaraj ,  Shankar Ganapathysubramanian ,  Richard J. Harries ,  Sankara J. Subramanian

Inventor： Mitul Modi ,  Sudarshan V. Rangaraj ,  Shankar Ganapathysubramanian ,  Richard J. Harries ,  Sankara J. Subramanian

IPC: H01L21/00 ,  H01L23/02

CPC classification number: H01L23/147 ,  H01L23/15 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.

Abstract translation: 两种材料（例如微电子管芯和安装衬底之间）的线性热膨胀系数（CTE）失配可能在材料的界面处引起应力。 在将管芯附接到安装基板的过程中存在的温度变化可能导致用于连接管芯和安装基板的电连接中的开裂和故障。 在安装基板中引入具有与模具CTE近似匹配的CTE的材料，以减少管芯和安装基板之间的电连接处的应力和开裂。 此外，该材料可以包括用于去耦电源的薄膜电容器。

公开(公告)号：US20080093114A1

公开(公告)日：2008-04-24

申请号：US11958191

申请日：2007-12-17

Applicant: Yu-Tuan Lee

Inventor： Yu-Tuan Lee

IPC: H05K1/18

CPC classification number: H05K3/4007 ,  H05K1/0306 ,  H05K1/111 ,  H05K3/1241 ,  H05K3/386 ,  H05K3/388 ,  H05K3/4667 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10674

Abstract: A circuit board according to the invention includes a glass substrate, an insulating layer, a plurality of protrusions and a first circuit layer. The insulating layer is disposed on the substrate and has a plurality of protrusion-positioning regions. The protrusion-positioning region is an opening or a concave. Each of the protrusions includes a polymer or a resin material and is disposed in the protrusion-positioning region and surrounded by the insulating layer. The first circuit layer is disposed on the insulating layer and has at least one trace line extending directly onto the protrusion.

Abstract translation: 根据本发明的电路板包括玻璃基板，绝缘层，多个突起和第一电路层。 绝缘层设置在基板上并且具有多个突起定位区域。 突出定位区域是开口或凹入。 每个突起包括聚合物或树脂材料，并且设置在突出定位区域中并被绝缘层包围。 第一电路层设置在绝缘层上并且具有直接延伸到突起上的至少一条迹线。

公开(公告)号：US20080047117A1

公开(公告)日：2008-02-28

申请号：US11923974

申请日：2007-10-25

Applicant: William Borland ,  Ian Burn ,  Jon Ihlefeld ,  Jon Maria ,  Seigi Suh

Inventor： William Borland ,  Ian Burn ,  Jon Ihlefeld ,  Jon Maria ,  Seigi Suh

IPC: H01G7/00 ,  H05K3/30

CPC classification number: H01L21/02197 ,  C01G23/006 ,  C01P2004/82 ,  C01P2006/40 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02337 ,  H01L21/31691 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  Y10T29/417 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T428/31678

Abstract: Described herein are methods for making articles comprising a dielectric layer formed from any solution composition that can form barium titanate during firing and containing manganese in an amount between 0.002 and 0.05 atom percent of the solution composition, wherein the dielectric layer has been formed on metal foil and fired in a reducing atmosphere.

Abstract translation: 本文描述了制备制品的方法，所述方法包括由任意溶液组合物形成的介电层，所述溶液组合物在焙烧期间可以形成钛酸钡并且含有0.002至0.05原子％的溶液组成的量，其中介电层已经形成在金属箔 并在还原气氛中开火。

公开(公告)号：US20080023219A1

公开(公告)日：2008-01-31

申请号：US11878452

申请日：2007-07-24

Applicant: Toshiyuki Yoshizawa ,  Masahiro Miyazaki ,  Akira Furuya ,  Masaomi Ishikura ,  Hajime Kuwajima

Inventor： Toshiyuki Yoshizawa ,  Masahiro Miyazaki ,  Akira Furuya ,  Masaomi Ishikura ,  Hajime Kuwajima

IPC: H01L27/01 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01L27/016 ,  H01L28/10 ,  H01L28/40 ,  H05K1/165 ,  H05K3/0023 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/1006

Abstract: An electronic component having: a substrate, a lower conductor layer provided on the substrate; an inorganic dielectric film that covers the lower conductor layer; and an upper conductor layer having an upper electrode portion provided on the inorganic dielectric film. The lower conductor layer has a lower electrode portion that together with the upper electrode portion and the inorganic dielectric film constitutes a capacitor, and a coil portion that constitutes an inductor. The entire inorganic dielectric film is formed integrally, and the lower conductor layer is in contact only with the substrate, inorganic dielectric film, and upper conductor layer.

Abstract translation: 一种电子部件，具有：基板，设置在基板上的下导体层; 覆盖下导体层的无机介电膜; 以及具有设置在无机介电膜上的上电极部的上导体层。 下导体层具有与上部电极部分和无机电介质膜一起构成电容器的下部电极部分和构成电感器的线圈部分。 整个无机介电膜一体形成，下导体层仅与基板，无机介电膜和上导体层接触。

公开(公告)号：US07323142B2

公开(公告)日：2008-01-29

申请号：US10038276

申请日：2002-01-02

Applicant: Shaun Pendo ,  Rajiv Shah ,  Edward Chernoff

Inventor： Shaun Pendo ,  Rajiv Shah ,  Edward Chernoff

IPC: G01N27/06 ,  G01N33/66

CPC classification number: H05K3/28 ,  A61B5/0006 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2203/082 ,  H05K2203/085 ,  H05K2203/1147 ,  H05K2203/1476 ,  H05K2203/1572 ,  H05K2203/308

Abstract: A substrate with hermetically sealed vias extending from one side of the substrate to another and a method for fabricating same. The vias may be filled with a conductive material such as, for example, a fritless ink. The conductive path formed by the conductive material aids in sealing one side of the substrate from another. One side of the substrate may include a sensing element and another side of the substrate may include sensing electronics.

Abstract translation: 具有从衬底的一侧延伸到另一侧的气密密封通孔的衬底及其制造方法。 通孔可以填充有导电材料，例如无油墨。 由导电材料形成的导电路径有助于将基板的一侧与另一侧密封。 衬底的一侧可以包括感测元件，并且衬底的另一侧可以包括感测电子器件。

公开(公告)号：US07284307B2

公开(公告)日：2007-10-23

申请号：US11253942

申请日：2005-10-19

Applicant: Tomoo Yamasaki ,  Noriyoshi Shimizu ,  Kiyoshi Oi

Inventor： Tomoo Yamasaki ,  Noriyoshi Shimizu ,  Kiyoshi Oi

IPC: H01G7/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/66 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/142 ,  H05K1/162 ,  H05K1/185 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2203/016 ,  H05K2203/0315 ,  Y10T29/43 ,  Y10T29/49002 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a wiring board, comprising the steps of: forming a first electrode layer having first and second opening portions, forming a dielectric layer formed on the first electrode layer and having third and fourth opening portions, forming a second electrode layer formed on the dielectric layer and having fifth and sixth opening portions, wherein the first electrode layer, the dielectric layer, and the second electrode layer form a capacitor; forming an insulating layer inside a first opening defined by the first, third, and fifth opening portions, and a second opening defined by the second, fourth, and sixth opening portions; using a laser beam having a processing diameter to form first and second via holes extending through the insulating layer formed inside the first and second openings, respectively; and forming first and second via wiring portions in the first and second via holes, respectively.

Abstract translation: 一种制造布线板的方法，包括以下步骤：形成具有第一和第二开口部分的第一电极层，形成在第一电极层上形成的第三和第四开口部分的电介质层，形成第二电极层， 所述电介质层具有第五和第六开口部分，其中所述第一电极层，所述电介质层和所述第二电极层形成电容器; 在由第一，第三和第五开口部分限定的第一开口内形成绝缘层，以及由第二开口部分，第四开口部分和第六开口部分限定的第二开口; 使用具有加工直径的激光束分别形成延伸穿过形成在第一和第二开口内的绝缘层的第一和第二通孔; 以及分别在第一和第二通孔中形成第一和第二通孔布线部分。