公开(公告)号：US07331794B2

公开(公告)日：2008-02-19

申请号：US11440069

申请日：2006-05-25

Applicant: Nicolas Imbert ,  Charles Chuc

Inventor： Nicolas Imbert ,  Charles Chuc

IPC: H01R12/00

CPC classification number: H05K7/1459 ,  H01R12/52 ,  H01R31/005 ,  H05K1/0289 ,  H05K1/14 ,  H05K1/148 ,  H05K7/1441 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09972

Abstract: A device (20) for interconnecting electrical bundles, includes a plurality of pluggable connection and cross-connect cards (34 to 38) for the electrical bundles. The device further includes a “main” printed circuit (28, 28b) fitted with connectors or slots (29 to 33) designed and arranged to receive the pluggable cards, the printed circuit having a plurality of parallel tracks (46), each enabling two tracks (61 to 63, 68) or tracks starters (70 to 72) provided respectively on two distinct pluggable cards plugged in the connectors of the main printed circuit to be put to the same potential, each of the parallel tracks (46) being in contact with a respective pin (50, 150) of a plurality of connectors of the main printed circuit.

Abstract translation: 用于互连电束的装置（20）包括用于电束的多个可插拔连接和交叉连接卡（34至38）。 该装置还包括装配有设计和布置成接收可插拔卡的连接器或槽（29至33）的“主”印刷电路（28,28b），印刷电路具有多个平行轨道（46），每个启用 两个轨道（61至63,68）或轨道起动器（70至72）分别设置在插入主印刷电路的连接器中以插入相同电位的两个不同的可插拔卡上，每个平行轨道（46）为 与主印刷电路的多个连接器的相应销（50,150）接触。

公开(公告)号：US20070295818A1

公开(公告)日：2007-12-27

申请号：US11473359

申请日：2006-06-22

Applicant: Yuan-Liang Li ,  Jayashree Kar ,  David G. Figueroa ,  Dong Zhong

Inventor： Yuan-Liang Li ,  Jayashree Kar ,  David G. Figueroa ,  Dong Zhong

IPC: G06K7/10

CPC classification number: H05K1/0265 ,  H05K1/0254 ,  H05K2201/044 ,  H05K2201/0784 ,  H05K2201/093 ,  H05K2201/0969

Abstract: A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.

Abstract translation: 包括供电电源插座，第一连接器电源插座和第二电源插座的电力平面，其中电源电极插座和第一连接器电源插座之间的第一电阻基本上等于第二电阻 在电源插座和第二连接器电源插座之间。

公开(公告)号：US07310240B2

公开(公告)日：2007-12-18

申请号：US10907420

申请日：2005-03-31

Applicant: Ryan M. Petersen

Inventor： Ryan M. Petersen

IPC: H05K7/00

CPC classification number: G06F1/26 ,  G11C5/147 ,  H05K1/0231 ,  H05K1/141 ,  H05K2201/044

Abstract: An apparatus for buffering power transients in a supply power for expansion cards inserted into expansion slots on a computer motherboard. The apparatus comprises a printed circuit board, a connector on the printed circuit board, and at least one capacitor on the printed circuit board. The connector is configured to fit into one of the expansion slots on the motherboard, and comprises at least one power pin and at least one ground pin. The at least one capacitor is connected to the power and ground pins of the connector and has sufficient capacitance to buffer power transients within the supply power to the expansion slots.

Abstract translation: 一种用于缓冲插入到计算机主板上的扩展槽中的扩展卡的供电电源瞬态的装置。 该装置包括印刷电路板，印刷电路板上的连接器和印刷电路板上的至少一个电容器。 连接器被配置成装配到主板上的一个扩展槽中，并且包括至少一个电源引脚和至少一个接地引脚。 至少一个电容器连接到连接器的电源和接地引脚，并且具有足够的电容以缓冲对扩展槽的供电的功率瞬变。

公开(公告)号：US07307862B2

公开(公告)日：2007-12-11

申请号：US10655927

申请日：2003-09-04

Applicant: Mike Cogdill ,  Idis Ramona Martinez ,  Derek Steven Schumacher

Inventor： Mike Cogdill ,  Idis Ramona Martinez ,  Derek Steven Schumacher

IPC: G11C5/06

CPC classification number: H05K1/0246 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1066 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2203/1572

Abstract: A circuit and system for improving signal integrity in a memory system. The circuit has a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled to the transmission line between the dampening impedance and the branch point. The transmission line has branches coupled to memory module interfaces. The branches have respective lengths between the branch point and the memory module interfaces to be configured symmetrically, wherein the branch point is at a point to balance signal transmission on the branches.

Abstract translation: 一种用于改善存储器系统中的信号完整性的电路和系统。 电路具有在驱动器和传输线的分支点之间具有阻尼阻抗的传输线。 电路还具有端接阻抗，其一端耦合到阻尼阻抗和分支点之间的传输线。 传输线具有耦合到存储器模块接口的分支。 分支在分支点和存储器模块接口之间具有对称配置的相应长度，其中分支点处于平衡分支上的信号传输的点。

公开(公告)号：US20070268087A9

公开(公告)日：2007-11-22

申请号：US10273410

申请日：2002-10-17

Applicant: Timothy Lemke ,  Richard Elco

Inventor： Timothy Lemke ,  Richard Elco

IPC: H01P5/02

CPC classification number: H05K1/024 ,  H01P3/08 ,  H05K1/14 ,  H05K3/10 ,  H05K3/202 ,  H05K2201/044 ,  H05K2201/09318

Abstract: A novel backplane interconnection system that is useful in the telecommunication and data process industries for ultra high speed backplane systems. It is capable of transmitting digital signals with bandwidths of 10 GHz and beyond. The invention provides high performance at a low cost of manufacture. It is suitable for use in a wide variety of system applications. One embodiment of the invention comprises an air dielectric and copper conductor matched impedance transmission line system that interconnects daughter cards in a conventional backplane configuration. The high speed transmission-line structure is continuous through the backplane-daughter card and return path. Such embodiment are also integrated with conventional printed circuit backplanes or be a stand-alone device.

Abstract translation: 一种新颖的背板互连系统，适用于超高速背板系统的电信和数据处理行业。 它能够传输10 GHz及以上带宽的数字信号。 本发明以低成本制造提供高性能。 适用于各种系统应用。 本发明的一个实施例包括在传统背板配置中互连子卡的空气电介质和铜导体匹配阻抗传输线系统。 高速传输线结构通过背板 - 子卡和返回路径是连续的。 这种实施例也与常规印刷电路底板集成或者是独立设备。

公开(公告)号：US20070262131A1

公开(公告)日：2007-11-15

申请号：US11433021

申请日：2006-05-11

Applicant: Janet Chua ,  Eit Yap

Inventor： Janet Chua ,  Eit Yap

IPC: G06F17/00

CPC classification number: H05K1/14 ,  H05K1/0269 ,  H05K2201/044 ,  H05K2201/09063 ,  H05K2201/10121

Abstract: An article and a method for testing the assembly of that article are disclosed. The article includes a plurality of modules, at least two of the modules are capable of being placed in two different positions in the article, each module having a correct position in the article. Each module includes an aperture at a location determined by the desired position for that module in the article. The apertures are placed such that the apertures will be aligned to form a transparent channel when the modules are arranged in a predetermined pattern with respect to one another, but not when arranged in any of the possible incorrect orders. The article can be tested for assembly errors by transmitting a test light signal into the first end and testing for light that traversed all of said first transparent channel.

Abstract translation: 公开了一种用于测试该物品装配的物品和方法。 该制品包括多个模块，至少两个模块能够被放置在制品中的两个不同位置，每个模块在制品中具有正确的位置。 每个模块包括在由该制品中的该模块的期望位置确定的位置处的孔。 这些孔被放置成使得当模块相对于彼此以预定图案布置时，孔将被对准以形成透明通道，但是当以任何可能的不正确顺序布置时，孔不被布置。 可以通过将测试光信号传输到第一端并测试穿过所有所述第一透明通道的光来测试物品的装配误差。

公开(公告)号：US20070230149A1

公开(公告)日：2007-10-04

申请号：US11807027

申请日：2007-05-24

Applicant: Matthew Bibee

Inventor： Matthew Bibee

IPC: H01R12/16

CPC classification number: H05K1/0219 ,  H01R12/523 ,  H01R13/6471 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/10189

Abstract: The embodiments of the present invention relate to an improved printed circuit board having additional rows of ground vias to reduce crosstalk in the board. A printed circuit board according to one embodiment of the present invention comprises a first row of vias and a second row of vias, each having a plurality of signal vias. The circuit board also comprises a plurality of rows of vias being coupled to a ground plane between the first row of signal vias and the second row of signal vias. According to one embodiment, the plurality of rows of vias being coupled to a ground plane comprise rows of vias having different sizes. Some of the vias are designed to receive a component, while others are generally smaller and designed to provide a return current path for the signal vias.

Abstract translation: 本发明的实施例涉及一种改进的印刷电路板，其具有附加的一排接地通孔，以减少电路板中的串扰。 根据本发明的一个实施例的印刷电路板包括第一行通孔和第二排通孔，每条通孔具有多个信号通路。 电路板还包括多个通孔的行，其耦合到第一行信号通孔和第二行信号通孔之间的接地平面。 根据一个实施例，耦合到接地平面的多排通孔包括具有不同尺寸的通孔列。 一些通孔被设计成接收组件，而其他通孔通常较小并被设计成为信号通路提供返回电流路径。

公开(公告)号：US20070216800A1

公开(公告)日：2007-09-20

申请号：US11691406

申请日：2007-03-26

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: H04N7/01

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A memory system includes a controller chip and a memory module coupled to the controller chip. A signal line carries a signal that traverses the signal line until reaching a termination at an end of the signal line. A clock line carries a clock signal that traverses the clock line to reach a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

Abstract translation: 存储器系统包括控制器芯片和耦合到控制器芯片的存储器模块。 信号线承载穿过信号线的信号，直到在信号线的末端达到终止。 时钟线承载穿过时钟线的时钟信号，以在时钟线的末端到达第二个终端。 模块包括连接到信号线和时钟线的第一存储器件，使得信号和时钟信号在基本相同的时间到达第一存储器件。 模块包括连接到信号线和时钟线的第二存储器件，使得信号和时钟信号在基本上相同的时间到达第二存储器件，并且在信号和时钟信号到达第一存储器件之后。

公开(公告)号：US20070207632A1

公开(公告)日：2007-09-06

申请号：US11367183

申请日：2006-03-03

Applicant: Steven Minich

Inventor： Steven Minich

IPC: H05K1/00

CPC classification number: H05K1/112 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/10189 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A first connector on a first side of a midplane circuit board may be offset from a second connector on a second side of the midplane circuit board. The first and second connectors may be substantially identical connectors, each with straight mounting contacts, to create an electrical interconnection therebetween without using a common signal via. Each side of the midplane may have the same footprint. Accordingly, substantially identical connectors may be used on both sides of the midplane circuit board.

Abstract translation: 在中平面电路板的第一侧上的第一连接器可以偏离中平面电路板的第二侧上的第二连接器。 第一和第二连接器可以是基本相同的连接器，每个连接器具有直的安装触点，以在它们之间形成电互连，而不使用公共信号通孔。 中平面的每一侧可能具有相同的足迹。 因此，可以在中平面电路板的两侧使用基本相同的连接器。

公开(公告)号：US20070156943A1

公开(公告)日：2007-07-05

申请号：US11685152

申请日：2007-03-12

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: G06F13/14

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A memory system includes a controller chip and a memory module coupled to the controller chip. A signal line carries a signal that traverses the signal line until reaching a termination at an end of the signal line. A clock line carries a clock signal that traverses the clock line to reach a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

Abstract translation: 存储器系统包括控制器芯片和耦合到控制器芯片的存储器模块。 信号线承载穿过信号线的信号，直到在信号线的末端达到终止。 时钟线承载穿过时钟线的时钟信号，以在时钟线的末端到达第二个终端。 模块包括连接到信号线和时钟线的第一存储器件，使得信号和时钟信号在基本相同的时间到达第一存储器件。 模块包括连接到信号线和时钟线的第二存储器件，使得信号和时钟信号在基本上相同的时间到达第二存储器件，并且在信号和时钟信号到达第一存储器件之后。