公开(公告)号：US20090163152A1

公开(公告)日：2009-06-25

申请号：US12329181

申请日：2008-12-05

Applicant: Mike Jiang

Inventor： Mike Jiang

IPC: H04B1/38

CPC classification number: H05K1/141 ,  H05K1/024 ,  H05K1/034 ,  H05K1/0373 ,  H05K1/142 ,  H05K2201/0209 ,  H05K2201/045 ,  H05K2201/09145 ,  H05K2201/10166 ,  H05K2203/167

Abstract: This description discloses a circuit board for a power amplifier that is able to keep a low temperature. In an example embodiment, the circuit board includes: an input board on its substrate, an output board on its substrate, and a power amplifier transistor acting as a bridge to connect the input board and the output board with each other. The substrate of the input board is made from a first kind of material, and the substrate of the output board is made from a second kind of material. The second kind of material has different performance (e.g., relatively better performance for both RF and heat dissipation) than that of the first kind of material. Moreover, this description discloses a power amplifier on the circuit board, a dual radio unit board having such a power amplifier, and a radio base station having such a dual radio unit board.

Abstract translation: 本说明书公开了能够保持低温的功率放大器的电路板。 在一个示例性实施例中，电路板包括：在其衬底上的输入板，其衬底上的输出板，以及充当用于将输入板和输出板彼此连接的桥的功率放大器晶体管。 输入板的基板由第一种材料制成，输出板的基板由第二种材料制成。 第二种材料具有与第一种材料不同的性能（例如，RF和散热的相对更好的性能）。 此外，该说明书公开了电路板上的功率放大器，具有这种功率放大器的双无线电单元板和具有这种双重无线电单元板的无线电基站。

公开(公告)号：US20090080164A1

公开(公告)日：2009-03-26

申请号：US11859601

申请日：2007-09-21

Applicant: Brian T. Purcell ,  Melvin K. Benedict

Inventor： Brian T. Purcell ,  Melvin K. Benedict

IPC: H05K1/14

CPC classification number: H05K1/148 ,  H05K1/141 ,  H05K2201/045 ,  H05K2201/10159

Abstract: A system in some embodiments includes a system having a memory module having a first board comprising a first plurality of memory receptacles configured to support a first plurality of in-line memory modules in an overlapping relationship with a second plurality of in-line memory modules disposed on a second board. Further, a method in some embodiments includes rotating first and second memory boards into a parallel configuration via a hinge coupling the first and second memory boards, and inserting the first and second memory boards into first and second board connectors simultaneously.

Abstract translation: 在一些实施例中的系统包括具有存储器模块的系统，该存储器模块具有第一板，所述第一板包括第一多个存储器插槽，其被配置为以与第二多个在线存储器模块布置的重叠关系支持第一组多个在线存储器模块 在第二板上。 此外，在一些实施例中的方法包括经由联接第一和第二存储器板的铰链将第一和第二存储器板旋转成并联配置，以及将第一和第二存储器板同时插入第一和第二板连接器。

公开(公告)号：US20090078456A1

公开(公告)日：2009-03-26

申请号：US12286012

申请日：2008-09-27

Applicant: William Macropoulos ,  Izzac Khayo ,  Greg Mendolia

Inventor： William Macropoulos ,  Izzac Khayo ,  Greg Mendolia

IPC: H01L21/50 ,  H01R12/04

CPC classification number: H05K1/144 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0206 ,  H05K1/0237 ,  H05K1/024 ,  H05K1/141 ,  H05K1/142 ,  H05K1/145 ,  H05K1/165 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0187 ,  H05K2201/045 ,  H05K2201/09972 ,  H05K2201/1031 ,  H05K2201/10636 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/0401

Abstract: At least an embodiment of the present technology provides a method of manufacturing a mechanically adapting interconnecting device for multi-substrate packages comprising placing a metal laminate on each side of a polymer composite, forming a channel in the metal laminate; and metallizing the laminate to create a metal connection inside the channel.

Abstract translation: 本技术的至少一个实施例提供了一种制造用于多基板封装的机械适应互连装置的方法，包括在金属层压板中形成通道的聚合物复合材料的每一侧上放置金属层压板; 并且对层压体进行金属化以在通道内形成金属连接。

公开(公告)号：US20090033337A1

公开(公告)日：2009-02-05

申请号：US11833418

申请日：2007-08-03

Applicant: Robert W. Pasco

Inventor： Robert W. Pasco

IPC: H01H31/02

CPC classification number: H05K3/3436 ,  G01R1/0416 ,  G01R31/2863 ,  H05K1/0306 ,  H05K1/141 ,  H05K3/3463 ,  H05K2201/045 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/162 ,  H05K2203/176 ,  Y02P70/613

Abstract: A testing substrate comprises internal circuitry connected to external contacts by wiring and meltable conductors are connected to the external contacts of the testing substrate. An interposer having substrate contacts on a first side is connected to the meltable conductors. The interposer is maintained apart from the testing substrate by the meltable conductors. The interposer comprises chip contacts on a second side opposite the first side. The chip contacts are adapted to temporarily connect to an integrated circuit chip being tested and burned-in. The chip contacts can have a different spacing than the substrate contacts. The interposer also includes conductive vias running from the first side to the second side and directly connecting the substrate contacts to the chip contacts.

Abstract translation: 测试基板包括通过布线连接到外部触点的内部电路，并且可熔化导体连接到测试基板的外部触点。 在第一侧具有衬底触点的插入件连接到可熔接导体。 通过可熔融导体将插入件与测试基板分开。 插入器包括在与第一侧相对的第二侧上的芯片触点。 芯片触点适于临时连接到被测试和烧录的集成电路芯片。 芯片触点可以具有与衬底触点不同的间隔。 插入器还包括从第一侧到第二侧延伸的导电通孔，并将衬底触点直接连接到芯片触点。

公开(公告)号：US20080288906A1

公开(公告)日：2008-11-20

申请号：US11787196

申请日：2007-04-13

Applicant: Troy D. Kopischke ,  John J. Michael ,  Kurt T. Larson ,  Gary F. Soebbing ,  Hans A. Rempel ,  Richard A. Kinnunen

Inventor： Troy D. Kopischke ,  John J. Michael ,  Kurt T. Larson ,  Gary F. Soebbing ,  Hans A. Rempel ,  Richard A. Kinnunen

IPC: G06F17/50 ,  H01L25/00

CPC classification number: G06F17/5068 ,  H05K1/141 ,  H05K3/0005 ,  H05K2201/045 ,  H05K2201/10689

Abstract: An electronic product includes a circuit board, an integrated system on module, and an application-specific module. The integrated system on module and the application-specific module are integrated with the circuit board. A method of forming the circuit board is disclosed, as well as a method of forming the electronic product.

Abstract translation: 电子产品包括电路板，模块上的集成系统和应用特定模块。 集成模块和应用专用模块与电路板集成在一起。 公开了形成电路板的方法，以及形成电子产品的方法。

公开(公告)号：US20080270649A1

公开(公告)日：2008-10-30

申请号：US11799169

申请日：2007-04-30

Applicant: Roger A. Pearson ,  Shane Ward

Inventor： Roger A. Pearson ,  Shane Ward

IPC: G06F13/00

CPC classification number: G06F13/409 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/045 ,  H05K2201/10159

Abstract: A multi-channel memory connection system comprises a circuit board comprising a plurality of memory connectors, at least one of the plurality of memory connectors configured to receive either a memory module or a memory riser, the at least one memory connector having at least two memory channels connected thereto through the circuit board.

Abstract translation: 多通道存储器连接系统包括包括多个存储器连接器的电路板，所述多个存储器连接器中的至少一个被配置为接收存储器模块或存储器提升器，所述至少一个存储器连接器具有至少两个存储器 通过电路板与其连接的通道。

公开(公告)号：US07436199B2

公开(公告)日：2008-10-14

申请号：US11976128

申请日：2007-10-22

Applicant: Woo-Seop Kim

Inventor： Woo-Seop Kim

IPC: G01R31/26 ,  G01R31/28 ,  H01L23/58

CPC classification number: G01R31/31905 ,  G01R1/0483 ,  G01R31/318505 ,  H01L2224/16225 ,  H01L2224/73253 ,  H05K1/141 ,  H05K1/145 ,  H05K2201/045 ,  H05K2201/10734

Abstract: A stack-type semiconductor package socket may include: a first package connection portion for connection with leads of a lowermost package of a stack-type semiconductor package; a second package connection portion for connection between pads of an odd-numbered package and leads of an even-numbered package, wherein the odd-numbered package and the even-numbered package are adjacent to each other; a lower case for fixing the first package connection portion; and an upper case for fixing the second package connection portion. A stack-type semiconductor package test system may include: a stack-type semiconductor package socket that includes first and second package connection portions; a printed circuit board electrically connected to leads of the lowermost package through the first package connection portion; and a test controller for receiving, outputting, or receiving and outputting signals from, to, or from and to the stack-type semiconductor package through the PCB and the stack-type semiconductor package socket.

Abstract translation: 堆叠型半导体封装插座可以包括：第一封装连接部分，用于连接堆叠型半导体封装的最下层封装的引线; 第二封装连接部分，用于在奇数封装的焊盘和偶数封装的引线之间连接，其中奇数封装和偶数封装彼此相邻; 用于固定第一包装连接部分的下壳体; 以及用于固定第二包装连接部分的上壳体。 叠层型半导体封装测试系统可以包括：堆叠型半导体封装插座，其包括第一和第二封装连接部分; 印刷电路板，其经由所述第一包装连接部电连接到所述最下包装的引线; 以及用于通过PCB和堆叠型半导体封装插座接收，输出或接收和输出从堆叠型半导体封装到堆叠型半导体封装的信号的测试控制器。

公开(公告)号：US20080101049A1

公开(公告)日：2008-05-01

申请号：US11586912

申请日：2006-10-26

Applicant: Brian W. Casto ,  John J. Retterer ,  Thomas L. Smith

Inventor： Brian W. Casto ,  John J. Retterer ,  Thomas L. Smith

IPC: H01R12/16

CPC classification number: H05K1/14 ,  G06F1/18 ,  H05K1/144 ,  H05K2201/044 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/10189

Abstract: In one exemplary embodiment, a system for supplying electrical connectivity to one or more circuit board based devices includes a backplane and at least one module. The backplane includes a mounting surface having a plurality of modular power connectors. The at least one module includes an interface portion, a power connection portion, and a circuit board. The power connection portion is configured to connect with the corresponding one of the plurality of modular power connectors. The circuit board includes a plurality of power-related electrical contacts and a plurality of data-related electrical contacts. At least one of the plurality of power-related electrical contacts is connected with the power connection portion, and at least one of the plurality of data-related electrical contacts is connected with the interface portion. The backplane is configured to connect with a power supply, such that the power supply supplies power to the at least one module through one of the modular power connectors when the at least one module is connected with the corresponding modular power connector.

Abstract translation: 在一个示例性实施例中，用于向一个或多个基于电路板的设备提供电连接的系统包括背板和至少一个模块。 背板包括具有多个模块化电源连接器的安装表面。 所述至少一个模块包括接口部分，电源连接部分和电路板。 电源连接部分被配置为与多个模块化电源连接器中的相应一个连接。 电路板包括多个功率相关的电触点和多个数据相关的电触点。 所述多个功率相关的电触头中的至少一个与所述电源连接部分连接，并且所述多个与数据有关的电触点中的至少一个与所述接口部分连接。 背板被配置为与电源连接，使得当至少一个模块与相应的模块化电源连接器连接时，电源通过模块化电源连接器之一向至少一个模块供电。

公开(公告)号：US07337522B2

公开(公告)日：2008-03-04

申请号：US11270317

申请日：2005-11-09

Applicant: Jason Engle ,  Rhandee Abrio ,  Julie Roslyn Bradbury-Bennett ,  Greg Allee ,  Kenneth Kledzik

Inventor： Jason Engle ,  Rhandee Abrio ,  Julie Roslyn Bradbury-Bennett ,  Greg Allee ,  Kenneth Kledzik

IPC: B23P23/00

CPC classification number: B23P23/00 ,  B23P19/00 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/1627 ,  H05K1/023 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/144 ,  H05K13/0434 ,  H05K13/0482 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/5137 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53261 ,  H01L2224/0401

Abstract: A method and apparatus for fabricating a three dimensional array of semiconductor chips is disclosed. The method uses a multiple step fabrication process that automates the surface mounting of semiconductor chips with unique chip carriers to achieve the three dimensional array of chips. The method can include the steps of depositing solder on one or more chip modules, placing and interconnecting low-cost components on the chip modules, and storing the preprocessed chip modules in pallets or in a tape and reel. Later these chip carriers may then be mounted on a circuit board, possibly over; for example, low and/or high cost components and then populated with low and/or high cost components. The apparatus includes a unique stackable chip module pallet and print fixture pedestal.

Abstract translation: 公开了一种用于制造半导体芯片的三维阵列的方法和装置。 该方法使用多步制造工艺，其使得具有独特芯片载体的半导体芯片的表面安装自动化以实现芯片的三维阵列。 该方法可以包括以下步骤：在一个或多个芯片模块上沉积焊料，将低成本部件放置和互连在芯片模块上，并将预处理的芯片模块存储在托盘中或磁带和卷轴中。 然后可以将这些芯片载体安装在电路板上， 例如低成本和/或高成本组件，然后填充低成本和/或高成本组件。 该设备包括独特的可堆叠芯片模块托盘和打印夹具底座。

公开(公告)号：US07226809B2

公开(公告)日：2007-06-05

申请号：US10440590

申请日：2003-05-19

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

IPC: H01L21/44

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10727

Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

Abstract translation: 多芯片组件包括在其外围边缘上具有外部连接器的半导体器件或半导体器件部件。 外部连接器通过沿相邻的未切割半导体器件或半导体器件部件之间的边界线形成通孔而形成，然后用导电材料电镀或填充孔。 当相邻的半导体器件或半导体器件部件彼此切断时，半导体器件之间的每个通孔中的导电材料被二等分。 多芯片组件的半导体器件和组件可以具有不同的尺寸，以及具有不同直径和间距的外部连接器阵列。 每个外部连接器的一端或两端可以电连接到另一个对准的外部连接器或另一个半导体器件或组件的接触区域。 以这种方式组装提供了低调的堆叠组件。