公开(公告)号：US07199462B2

公开(公告)日：2007-04-03

申请号：US11133727

申请日：2005-05-20

Applicant: Chang-soo Jang ,  Jae-chul Ryu ,  Dong-kwan Won

Inventor： Chang-soo Jang ,  Jae-chul Ryu ,  Dong-kwan Won

IPC: H01L23/12

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K3/0052 ,  H05K3/28 ,  H05K2201/068 ,  H05K2201/09781 ,  H05K2203/1572 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A parent or master substrate for a semiconductor package is provided, which can provide a plurality of unit substrates by cutting into pieces for producing a semiconductor device. The parent substrate includes an insulation layer, conductor patterns formed on first and second surfaces of the insulation layer, and PSR (photo solder resist) layers respectively formed on the first and second surfaces of the insulation layers and covering the conductor patterns. The parent substrate includes an upper part and a lower part divided by a reference surface which passes through the center of the insulation layer. When an equivalent thermal expansion coefficient αupper of the upper part is defined by the Equation of α upper = ∑ i = 1 n ⁢ α i × E i × v i ∑ i = 1 n ⁢ E i × v i , where αi is respective thermal expansion coefficients of, Ei is respective elastic moduli of, and vi is respective volume ratios of first through nth components constituting the upper part (e.g., insulation layer, conductor patterns, and PSR layers of the upper part), and an equivalent thermal expansion coefficient αlower of the lower part is defined by the Equation of α lower = ∑ j = 1 m ⁢ α j × E j × v j ∑ j = 1 m ⁢ E j × v j , where αj is respective thermal expansion coefficients of, Ej is respective elastic moduli of, and vj is respective volume ratios of first through mth components constituting the lower part (e.g., insulation layer, conductor patterns, and PSR layers of the lower part), a equivalent thermal expansion ratio (αupper/αlower) of αupper to αlower is selected to be within a range of 0.975 through 1.165.

Abstract translation: 提供了一种用于半导体封装的母板或母板，其可以通过切割成用于制造半导体器件的片来提供多个单元基板。 母基板包括绝缘层，形成在绝缘层的第一和第二表面上的导体图案，以及分别形成在绝缘层的第一和第二表面上并覆盖导体图案的PSR（光阻焊剂）层。 母基片包括由穿过绝缘层的中心的参考表面划分的上部和下部。 当上部的等效热膨胀系数α<上限由等式定义时

公开(公告)号：US20070042202A1

公开(公告)日：2007-02-22

申请号：US10550582

申请日：2004-03-25

Applicant: Soon-yong Park ,  You-jin Kyung ,  Heon-sik Song ,  Byeong-in Ahn ,  Joo-eun Ko ,  Yong-jun Park ,  Se-myung Jang

Inventor： Soon-yong Park ,  You-jin Kyung ,  Heon-sik Song ,  Byeong-in Ahn ,  Joo-eun Ko ,  Yong-jun Park ,  Se-myung Jang

IPC: B32B15/08

CPC classification number: B32B15/08 ,  B32B27/08 ,  B32B27/281 ,  B32B2307/308 ,  B32B2307/734 ,  B32B2457/08 ,  H05K1/0346 ,  H05K1/036 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/068 ,  Y10T428/31681 ,  Y10T428/31721

Abstract: The present invention relates to a double-sided metallic laminate for a printed circuit board and a method for manufacturing the same. The double-sided metallic laminate which comprises a metallic layer at one side, a resin layer of a polyimide for improving adhesion with a metal, a resin layer of a low expansion polyimide having a thermal expansion coefficient of 5×10-6 to 2.5×10-5/iÉ and a metallic layer at the other side, has excellent flexibility and thermal resistance, can prevent curl and is securely laminated, particularly without the use of an adhesive. Therefore, it is suitable for a printed circuit board of a small size electric appliance.

Abstract translation: 本发明涉及一种用于印刷电路板的双面金属层压板及其制造方法。 一侧包含金属层的双面金属层压体，用于提高与金属的粘合性的聚酰亚胺树脂层，热膨胀系数为5×10 -6〜2.5×10 -5的低膨胀性聚酰亚胺树脂层 另一侧的金属层具有优异的柔软性和耐热性，可以防止卷曲并且可靠地层压，特别是不使用粘合剂。 因此，适用于小型电器的印刷电路板。

公开(公告)号：US20060286828A1

公开(公告)日：2006-12-21

申请号：US11461749

申请日：2006-08-01

Applicant: Igor Khandros

Inventor： Igor Khandros

IPC: H01R12/00

CPC classification number: H05K7/1069 ,  B23K1/0016 ,  B23K2101/40 ,  C23C18/161 ,  C25D7/12 ,  G01R1/0466 ,  G01R1/06711 ,  G01R1/06761 ,  G01R1/07307 ,  G01R3/00 ,  G01R31/2884 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6715 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45116 ,  H01L2224/45117 ,  H01L2224/4512 ,  H01L2224/45123 ,  H01L2224/45124 ,  H01L2224/45138 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45163 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45176 ,  H01L2224/4554 ,  H01L2224/4556 ,  H01L2224/456 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4015 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49174 ,  Y10T29/49179 ,  Y10T29/49204 ,  Y10T29/49222 ,  Y10T29/49224 ,  Y10T29/49609 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/0102

Abstract: A contact structure can comprise a core structure on a substrate and over coat material on the core structure. The over coat material can be harder or have a greater yield strength than the material of the core structure. The core structure can be formed by attaching a wire to the substrate and spooling the wire out from a spool. While spooling the wire out, the spool can be moved to impart a desired shape to the wire. The wire can be severed from the spool and over coated. As an alternative, the wire need not be over coated. The substrate can be an electronic device, such as a semiconductor die.

Abstract translation: 接触结构可以包括基底上的芯结构和芯结构上的外涂层材料。 外涂层材料可以比芯结构的材料更硬或具有更大的屈服强度。 芯结构可以通过将线附接到基底并且将线从线轴缠绕而形成。 在将电线绕出线的同时，可以使线轴移动以向导线赋予期望的形状。 电线可以从线轴上被切断并且被覆盖。 作为替代，电线不需要过度涂覆。 基板可以是诸如半导体管芯的电子器件。

公开(公告)号：US07143500B2

公开(公告)日：2006-12-05

申请号：US09888689

申请日：2001-06-25

Applicant: Phillip E. Byrd

Inventor： Phillip E. Byrd

IPC: H01H1/58

CPC classification number: G01R1/06766 ,  G01R1/07371 ,  G01R3/00 ,  G01R31/2886 ,  H05K1/0293 ,  H05K1/09 ,  H05K1/167 ,  H05K2201/068 ,  H05K2201/10053 ,  H05K2201/10181 ,  Y10T29/49004 ,  Y10T29/49005 ,  Y10T29/49107 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204

Abstract: Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective fuses are provided in electrical communication with conductive traces and probe elements (e.g., probe needles) of a probe card. The fuses may be active or passive fuses, and are preferably self-resetting, repairable, and/or replaceable. Typically, the fuses will be interposed in, or located adjacent to, conductive traces residing over a surface of the probe card. Methods of fabricating a probe card are provided, as well as various probe card configurations. A semiconductor die testing system using the probe card is also provided.

Abstract translation: 探头卡配置有适用于半导体裸片电气测试的保护电路，而不会损坏探针卡。 提供保护性熔丝与探针卡的导电迹线和探针元件（例如探针）电连通。 保险丝可以是有源或被动保险丝，并且优选地是自复位，可修复和/或可更换的。 通常，保险丝将被置于位于探针卡的表面上方的导电迹线中或邻近其上。 提供制造探针卡的方法以及各种探针卡配置。 还提供了使用探针卡的半导体管芯测试系统。

公开(公告)号：US07140883B2

公开(公告)日：2006-11-28

申请号：US10692114

申请日：2003-10-23

Applicant: Igor Y. Khandros ,  Benjamin N. Eldridge ,  Gaetan L. Mathieu ,  Thomas H. Dozier, II ,  William D. Smith

Inventor： Igor Y. Khandros ,  Benjamin N. Eldridge ,  Gaetan L. Mathieu ,  Thomas H. Dozier, II ,  William D. Smith

IPC: G01R31/02

CPC classification number: H05K3/4015 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/06711 ,  G01R1/06716 ,  G01R1/07342 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2884 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/49208 ,  Y10T29/49222 ,  H01L2924/00 ,  H01L2224/48

Abstract: An interconnection apparatus and a method of forming an interconnection apparatus. Contact structures are attached to or formed on a first substrate. The first substrate is attached to a second substrate, which is larger than the first substrate. Multiple such first substrates may be attached to the second substrate in order to create an array of contact structures. Each contact structure may be elongate and resilient and may comprise a core that is over coated with a material that imparts desired structural properties to the contact structure.

Abstract translation: 一种互连装置和形成互连装置的方法。 接触结构附着在第一基底上或形成在第一基底上。 第一衬底附接到比第一衬底大的第二衬底。 可以将多个这样的第一基板附接到第二基板，以便产生接触结构的阵列。 每个接触结构可以是细长的和弹性的，并且可以包括在涂覆有向接触结构赋予期望的结构特性的材料的芯上。

公开(公告)号：US20060205273A1

公开(公告)日：2006-09-14

申请号：US10906810

申请日：2005-03-08

Applicant: William Brodsky ,  James Busby ,  Bruce Chamberlin ,  Mitchell Ferrill ,  Robin Susko ,  James Wilcox

Inventor： William Brodsky ,  James Busby ,  Bruce Chamberlin ,  Mitchell Ferrill ,  Robin Susko ,  James Wilcox

IPC: H01R13/40

CPC classification number: H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0501 ,  H01L2224/05011 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30107 ,  H01R4/01 ,  H01R12/52 ,  H05K3/325 ,  H05K2201/068 ,  H05K2201/209 ,  H05K2203/1105 ,  H01L2224/05099

Abstract: A method and structure is disclosed for forming a removable interconnect for semiconductor packages, where the connector is adapted to repeatedly change from a first shape into a second shape upon being subjected to a temperature change and to repeatedly return to the first shape when not being subjected to the temperature change. The connector can be disconnected when the connector is in its second shape and the connector cannot be disconnected when the connector is in its first shape.

Abstract translation: 公开了一种用于形成用于半导体封装的可移除互连的方法和结构，其中连接器适于在经受温度变化时从第一形状重复地变为第二形状，并且在不受影响时重复地返回到第一形状 到温度变化。 当连接器处于其第二形状时，连接器可以断开，并且当连接器处于其第一形状时连接器不能断开。

公开(公告)号：US20060204733A1

公开(公告)日：2006-09-14

申请号：US11362516

申请日：2006-02-27

Applicant: Makoto Murai ,  Ryosuke Usui

Inventor： Makoto Murai ,  Ryosuke Usui

IPC: B32B3/00

CPC classification number: C23C28/00 ,  C23C28/322 ,  C23C28/345 ,  H01L23/3121 ,  H01L23/3733 ,  H01L23/3735 ,  H01L23/3737 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/284 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/0269 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0315 ,  Y10T428/24331 ,  Y10T428/24917 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: The present invention provides a circuit device capable of controlling deformation of a circuit device while preventing an insulating layer from peeling from a substrate. The circuit device includes a substrate, an insulating layer formed on the substrate, a filler filled into the insulating layer, a conductive layer formed on the insulating layer, and a circuit element formed on the conductive layer, wherein an average particle diameter of the filler filled into the insulating layer is controlled so that a Young's modulus of a part of the insulating layer on a substrate side can be smaller than a Young's modulus of a part of the insulating layer on an opposite side relative to the substrate side.

公开(公告)号：US20060185141A1

公开(公告)日：2006-08-24

申请号：US11410984

申请日：2006-04-26

Applicant: Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

Inventor： Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

IPC: H01G7/00 ,  H01K3/10

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/0041 ,  H05K3/0044 ,  H05K3/388 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/09763 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/1338 ,  H05K2203/1581 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

公开(公告)号：US07094975B2

公开(公告)日：2006-08-22

申请号：US10717839

申请日：2003-11-20

Applicant: Suresh K. Chengalva ,  David W. Ihms ,  Bruce A. Myers

Inventor： Suresh K. Chengalva ,  David W. Ihms ,  Bruce A. Myers

IPC: H05K1/03

CPC classification number: H05K1/0206 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/0271 ,  H05K3/0061 ,  H05K2201/068 ,  H05K2201/10204 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/2009

Abstract: A circuit board assembly comprising a laminate substrate and a surface mount device having a CTE less than that of the laminate substrate and attached with at least one solder joint to a first surface of the laminate substrate. The assembly further includes a localized stiffener attached to a second surface of the laminate substrate so as to be directly opposite the circuit device. The localized stiffener is formed of a material and is shaped so that, when attached to the laminate substrate, the stiffener is capable of increasing the thermal cycle fatigue life of the one or more solder joints that attach the device to the substrate.

Abstract translation: 一种电路板组件，包括层压基板和表面安装装置，所述表面安装装置的CTE小于层压基板的CTE，并且与至少一个焊接接头连接到层叠基板的第一表面。 组件还包括附着到层叠基板的第二表面以便与电路装置直接相对的局部加强件。 局部加强件由材料形成并且被成形为使得当附接到层叠基板时，加强件能够增加将该装置附接到基板的一个或多个焊点的热循环疲劳寿命。

公开(公告)号：US20060180639A1

公开(公告)日：2006-08-17

申请号：US11059596

申请日：2005-02-16

Applicant: Vahid Goudarzi ,  Julio Abdala ,  Gulten Goudarzi

Inventor： Vahid Goudarzi ,  Julio Abdala ,  Gulten Goudarzi

IPC: B23K31/02 ,  C22C13/00

CPC classification number: H05K3/3436 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/203 ,  B23K2101/42 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/068 ,  H05K2203/043 ,  H05K2203/0485 ,  Y02P70/613

Abstract: A method (80) of reducing stress between substrates of differing materials includes the steps of applying (82) solder (16) on a first substrate (14), reflowing (84) the solder on the first substrate to form a cladded substrate (30), applying (85) a medium such as flux or solder on a second substrate (42) having a substantially different coefficient of thermal expansion than the first substrate, placing (86) the cladded substrate on the second substrate, and reflowing (88) the cladded substrate and the second substrate such that thermal stress caused by the substantially different coefficient of thermal expansion between the first and second substrates is limited to when a temperature approximately reaches below a solidus temperature of the solder on the first substrate.

Abstract translation: 减少不同材料的衬底之间的应力的方法（80）包括以下步骤：在第一衬底（14）上施加（82）焊料（16），在第一衬底上回流（84）焊料以形成包覆衬底（30） 将具有基本上不同于第一基板的热膨胀系数的第二基板（42）施加（85）诸如焊剂或焊料的介质，将包覆的基板放置在第二基板上，并且回流（88） 包覆基板和第二基板使得由第一和第二基板之间的基本上不同的热膨胀系数引起的热应力被限制在当温度近似低于第一基板上的焊料的固相线温度时。