公开(公告)号：US07381098B2

公开(公告)日：2008-06-03

申请号：US11402544

申请日：2006-04-11

Applicant: Bernard Harold Hammond, Jr. ,  David Patrick Murray ,  Ian Robert George

Inventor： Bernard Harold Hammond, Jr. ,  David Patrick Murray ,  Ian Robert George

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R4/2416 ,  H01R13/6658 ,  H01R13/719 ,  H01R24/64 ,  H01R2107/00 ,  H05K1/0228 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49117 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a multi-zone crosstalk compensation arrangement for reducing crosstalk at the jack.

Abstract translation: 本公开涉及一种电信插孔，其包括具有用于接收插头的端口的壳体。 千斤顶还包括多个接触弹簧，其适于当插头插入壳体的端口时与插头电接触，以及多个用于将插线端接到插座的导线终端触头。 千斤顶还包括将接触弹簧电连接到导线终端触点的电路板。 电路板包括用于减少插座处串扰的多区串扰补偿装置。

公开(公告)号：US20080099238A1

公开(公告)日：2008-05-01

申请号：US11925370

申请日：2007-10-26

Applicant: Srdjan Djordjevic

Inventor： Srdjan Djordjevic

IPC: H05K9/00 ,  H01R43/00 ,  H05K1/11

CPC classification number: H05K1/0237 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/117 ,  H05K1/181 ,  H05K2201/0723 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  Y10T29/49117

Abstract: A printed circuit board for a memory module is disclosed. The printed circuit board provides inner layers, at least one middle layer with at least one large-area conductor structure for guiding a respective substantially constant electric potential. On a first and/or second inner layer directly above or below the middle layer, first or second high speed conductor structures are arranged to guide first or second high speed signals over the largest share of their guidance on the printed circuit board. Arranged on a top and/or bottom layer are: contacting conductor structures for at least one device, printed circuit board input and printed circuit board output contact terminals and short conductor structures which are each connected with predetermined ones of the printed circuit board input and/or printed circuit board output contact terminals or predetermined ones of the first and/or second high speed conductor structures through vias between the layers.

Abstract translation: 公开了一种用于存储器模块的印刷电路板。 印刷电路板提供内层，至少一个具有至少一个大面积导体结构的中间层，用于引导相应的基本恒定的电位。 在中间层正上方或下方的第一和/或第二内层上，布置第一或第二高速导体结构，以便在印刷电路板上引导第一或第二高速信号的引导的最大份额上。 布置在顶部和/或底层上的是：用于至少一个装置的接触导体结构，印刷电路板输入和印刷电路板输出接触端子和短导体结构，其各自与印刷电路板输入和/ 或印刷电路板输出接触端子或第一和/或第二高速导体结构中的预定的通过层之间的通孔。

公开(公告)号：US20080088007A1

公开(公告)日：2008-04-17

申请号：US11580444

申请日：2006-10-13

Applicant: Minh van Quach ,  Nurwati S. Devnani ,  Robert B. Manley

Inventor： Minh van Quach ,  Nurwati S. Devnani ,  Robert B. Manley

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H05K1/0219 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19032 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K2201/0715 ,  H05K2201/09236 ,  H01L2924/00

Abstract: Systems, devices and methods are disclosed herein for reducing crosstalk between pairs of differential signal conductors. One or more ground traces connected to one or more over- or under-lying ground planes by vias are located between pairs of differential signal conductors. The electrical shielding provided by the combination of the one or more ground traces and the one or more ground planes results in reduced cross-talk between different pairs of differential signal conductors, and facilitates high-speed data rates between integrated circuits and printed circuit boards. In a preferred embodiment, such ground traces and ground planes are employed in HiTCE packaging containing multiple pairs of differential signal conductors.

Abstract translation: 本文公开了用于减少差分信号导体对之间的串扰的系统，装置和方法。 通过通孔连接到一个或多个过或不足的接地层的一个或多个接地迹线位于差分信号导体对之间。 由一个或多个接地迹线和一个或多个接地平面的组合提供的电屏蔽导致不同差分信号导体对之间的串扰减少，并且有助于集成电路和印刷电路板之间的高速数据速率。 在优选实施例中，在包含多对差分信号导体的HiTCE封装中使用这种接地迹线和接地层。

公开(公告)号：US20080075070A1

公开(公告)日：2008-03-27

申请号：US11978810

申请日：2007-10-30

Applicant: Joel Goergen

Inventor： Joel Goergen

IPC: H04L12/50

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: A circuit board comprises signaling through-holes that pass through a plurality of layers, including signal trace and digital ground plane layers, and power reference plane layers. Clearances are set to achieve a desired impedance characteristic for the through-holes. At a power reference plane layer, the clearance is defined around multiple neighboring through-holes.

Abstract translation: 电路板包括通过多个层的信令通孔，包括信号迹线和数字接地层以及功率参考平面层。 设定间隙以实现通孔所需的阻抗特性。 在功率参考平面层上，间隙围绕多个相邻的通孔限定。

公开(公告)号：US07346880B2

公开(公告)日：2008-03-18

申请号：US11171576

申请日：2005-06-30

Applicant: Choupin B. Huang ,  Charles T. Ballou ,  Ramesh K. R. Velugoti ,  Drin-Guang W. Chen

Inventor： Choupin B. Huang ,  Charles T. Ballou ,  Ramesh K. R. Velugoti ,  Drin-Guang W. Chen

IPC: G06F17/50

CPC classification number: G06F1/10 ,  H05K1/023 ,  H05K1/0245 ,  H05K1/0246 ,  H05K1/0248 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10689

Abstract: Methods and arrangements to gang differential clock signals to attenuate pin-to-pin output skew for a clock driver are disclosed. Embodiments may comprise a pattern of conductors to interconnect output pins for differential clock signals with termination resistors. The pattern of conductors comprises a group of conductors for a positive clock (p-clock) signal and a group of conductors for a negative clock (n-clock) signal. The conductors for the p-clock signal intersect at a gang point between the output pins and pads for the termination resistors. Similarly, the conductors for the n-clock signals intersect at a gang point between the pins and the pads. In many embodiments, the distance between the pins and pads may be approximately 120 mils. In further embodiments, the distance may be longer or shorter than 120 mils. Other embodiments are disclosed and claimed.

Abstract translation: 公开了组合差分时钟信号以衰减时钟驱动器的引脚到引脚输出偏移的方法和布置。 实施例可以包括用于将用于差分时钟信号的输出引脚互连到终端电阻器的导体图案。 导体图案包括用于正时钟（p时钟）信号的一组导体和用于负时钟（n时钟）信号的一组导体。 用于p时钟信号的导体在终端电阻的输出引脚和焊盘之间的帮派点处相交。 类似地，n时钟信号的导体在引脚和焊盘之间的帮派点相交。 在许多实施例中，引脚和焊盘之间的距离可以是大约120密耳。 在另外的实施例中，该距离可以长于或短于120密耳。 公开和要求保护其他实施例。

公开(公告)号：US20080062666A1

公开(公告)日：2008-03-13

申请号：US11893043

申请日：2007-08-13

Applicant: Myong-Bin Lim ,  Jae-Han Lee ,  Sun-Kyu Son ,  In-Yong Hwang

Inventor： Myong-Bin Lim ,  Jae-Han Lee ,  Sun-Kyu Son ,  In-Yong Hwang

IPC: G02F1/133 ,  H05K7/00

CPC classification number: H05K1/0216 ,  G02F1/13452 ,  H05K1/025 ,  H05K1/189 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09781 ,  H05K2201/10136 ,  H05K2201/10681

Abstract: A signal transfer member for a liquid crystal display (LCD) apparatus includes a power line for receiving power from an external source and for driving a semiconductor chip disposed on the transfer member or the display apparatus. The power line is bent so as to incorporate a serpentine structure, which enables the length of the power line to be easily adjusted and results in the line being longer than a power line formed with a relatively straight structure. Accordingly, the length of the power line can be adjusted to take into account the respective impedances of the chip and the external source so as to suppress electromagnetic waves in the power line. This prevents the creation of noise, distortion of signals, damage to the semiconductor chip, and disconnection of the input interconnection thereof that are caused by the electromagnetic waves, so that product yields are thereby improved.

Abstract translation: 用于液晶显示器（LCD）装置的信号传递部件包括用于从外部源接收电力并用于驱动设置在转印部件或显示装置上的半导体芯片的电力线。 电力线被弯曲以包括蛇形结构，这使得能够容易地调节电力线的长度，并且导致线比形成有相对直的结构的电力线更长。 因此，可以调整电力线的长度以考虑芯片和外部源的各自的阻抗，以便抑制电力线中的电磁波。 这防止了由电磁波引起的噪声，信号失真，半导体芯片的损坏和输入互连的断开，从而提高了产品的产量。

公开(公告)号：US20080062658A1

公开(公告)日：2008-03-13

申请号：US11852406

申请日：2007-09-10

Applicant: YOSHIO OOWAKI

Inventor： YOSHIO OOWAKI

IPC: H05K1/02 ,  H05K5/02

CPC classification number: H05K1/028 ,  H05K1/0219 ,  H05K1/0224 ,  H05K2201/09236 ,  H05K2201/09781

Abstract: According to the invention, information processing equipment using a flexible printed-circuit board which does not lose bendability with repeated opening and closing of a display unit, and which suppresses radiation noise from signal wiring is provided.In the configuration of the invention, a first cover film is formed to cover a wiring layer on a first surface of a base film, and a second cover film is formed to cover a wiring layer on a second surface of the base film. Portions of the second cover film and the underlying wiring layer on the second surface in the loop formation region are discontinuously removed in the inward-bending area of the loop, and the base film is exposed in the removed parts. The wiring layer underneath the remaining second cover film, which is not removed, and the wiring layer on the first surface of the base film are electrically connected via through holes penetrating the base film.

Abstract translation: 根据本发明，提供了使用柔性印刷电路板的信息处理设备，其通过重复打开和关闭显示单元而不失去弯曲性，并且抑制了来自信号布线的辐射噪声。 在本发明的结构中，形成第一覆盖膜以覆盖基膜的第一表面上的布线层，并且形成第二覆盖膜以覆盖基膜的第二表面上的布线层。 第二覆盖膜的一部分和环形成区域中的第二表面上的底层布线层在环的向内弯曲区域中不连续地移除，并且基膜在去除部分中露出。 未除去的剩余的第二覆盖膜下面的布线层和基膜的第一表面上的布线层通过穿透基膜的通孔电连接。

公开(公告)号：US07343576B2

公开(公告)日：2008-03-11

申请号：US11304267

申请日：2005-12-14

Applicant: Gary A. Brist ,  Gary B. Long ,  William O. Alger ,  Carlos Mejia ,  Bryce Horine

Inventor： Gary A. Brist ,  Gary B. Long ,  William O. Alger ,  Carlos Mejia ,  Bryce Horine

IPC: G06F17/50

CPC classification number: H05K1/0366 ,  G06F17/5077 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/0248 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09263

Abstract: A method and apparatus for reducing timing skew between conductor traces. A dielectric medium made of a resin reinforced with a fabric is provided. The fabric includes a first plurality of yarns running parallel to a first axis and a second plurality of yarns running parallel to a second axis. The first plurality of yarns are separated by a first weave pitch and the second plurality of yarns separated by a second weave pitch. At least two conductor traces are formed on the dielectric medium. The conductor traces are positioned on the dielectric medium such that the conductor traces each have substantially similar effective dielectric constants.

Abstract translation: 一种用于减少导体迹线之间的定时偏差的方法和装置。 提供由用织物增强的树脂制成的电介质。 织物包括平行于第一轴线延伸的第一组多根纱线和平行于第二轴线延伸的第二组纱线。 第一组多个纱线由第一编织间距分开，第二组纱线由第二编织间距分开。 在电介质上形成至少两根导体迹线。 导电迹线位于介电介质上，使得导体迹线各自具有基本相似的有效介电常数。

公开(公告)号：US07336139B2

公开(公告)日：2008-02-26

申请号：US11588640

申请日：2006-10-27

Applicant: James Leroy Blair ,  Oswin M. Schreiber ,  Jeffrey Thomas Smith

Inventor： James Leroy Blair ,  Oswin M. Schreiber ,  Jeffrey Thomas Smith

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01P3/006 ,  H01P3/08 ,  H05K1/0237 ,  H05K1/0393 ,  H05K1/147 ,  H05K3/222 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/10492 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A high speed flexible interconnect cable includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The transmission line structure may be realized as a grounded coplanar waveguide structure. The cable can be coupled to destination components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector packages.

Abstract translation: 高速柔性互连电缆包括多个导电层和多个电介质层。 位于导电层上的导电信号迹线与电介质层结合形成一个或多个高速电传输线结构。 传输线结构可以被实现为接地的共面波导结构。 电缆可以使用各种连接技术耦合到目标组件。 电缆也可以用任何数量的已知或标准的连接器封装端接。

公开(公告)号：US07331794B2

公开(公告)日：2008-02-19

申请号：US11440069

申请日：2006-05-25

Applicant: Nicolas Imbert ,  Charles Chuc

Inventor： Nicolas Imbert ,  Charles Chuc

IPC: H01R12/00

CPC classification number: H05K7/1459 ,  H01R12/52 ,  H01R31/005 ,  H05K1/0289 ,  H05K1/14 ,  H05K1/148 ,  H05K7/1441 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09972

Abstract: A device (20) for interconnecting electrical bundles, includes a plurality of pluggable connection and cross-connect cards (34 to 38) for the electrical bundles. The device further includes a “main” printed circuit (28, 28b) fitted with connectors or slots (29 to 33) designed and arranged to receive the pluggable cards, the printed circuit having a plurality of parallel tracks (46), each enabling two tracks (61 to 63, 68) or tracks starters (70 to 72) provided respectively on two distinct pluggable cards plugged in the connectors of the main printed circuit to be put to the same potential, each of the parallel tracks (46) being in contact with a respective pin (50, 150) of a plurality of connectors of the main printed circuit.

Abstract translation: 用于互连电束的装置（20）包括用于电束的多个可插拔连接和交叉连接卡（34至38）。 该装置还包括装配有设计和布置成接收可插拔卡的连接器或槽（29至33）的“主”印刷电路（28,28b），印刷电路具有多个平行轨道（46），每个启用 两个轨道（61至63,68）或轨道起动器（70至72）分别设置在插入主印刷电路的连接器中以插入相同电位的两个不同的可插拔卡上，每个平行轨道（46）为 与主印刷电路的多个连接器的相应销（50,150）接触。