公开(公告)号：US12082346B2

公开(公告)日：2024-09-03

申请号：US18175898

申请日：2023-02-28

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Masahiro Kyozuka

IPC: H05K1/02 ,  H05K1/05 ,  H05K3/00

CPC classification number: H05K3/0011 ,  H05K1/0271 ,  H05K1/05 ,  H05K2201/093 ,  H05K2201/09372 ,  H05K2201/10204

Abstract: A wiring board includes a first insulating layer, a pad formed on one surface of the first insulating layer, a second insulating layer, formed on the one surface of the first insulating layer, and including an opening exposing the pad, and a reinforcing metal layer formed in contact with the first insulating layer, and provided around the pad so as to be separated from the pad in a plan view. The pad is disposed inside the opening without making contact with the second insulating layer. An end, on a side of the first insulating layer, in a portion of an inner side surface of the opening of the second insulating layer makes contact with the reinforcing metal layer, and an end in another portion of the inner side surface of the opening of the second insulating layer makes contact with the one surface of the first insulating layer.

公开(公告)号：US12052819B2

公开(公告)日：2024-07-30

申请号：US17707196

申请日：2022-03-29

Applicant: IBIDEN CO., LTD.

Inventor： Tomohiro Kobayashi

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/11 ,  H05K1/111 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/093

Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including pads, a solder resist layer formed on the base layer such that the solder resist layer is covering the conductor layer and has openings exposing the pads, and plating bumps formed on the pads such that each plating bump includes a base plating layer formed in a respective one of the openings, an intermediate layer formed on the base plating layer, and a top plating layer formed on the intermediate layer. The plating bumps are formed such that the base plating layer has a side surface including a portion protruding from the solder resist layer, that the intermediate layer has a thickness in a range of 2.7 to 7.0 μm, and that the top plating layer has a hemispherical shape and is covering only an upper surface of the intermediate layer.

公开(公告)号：US11903122B2

公开(公告)日：2024-02-13

申请号：US17430940

申请日：2020-02-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Dong Huang

IPC: H05K1/02 ,  H01F27/28 ,  H05K1/14 ,  H05K1/18

CPC classification number: H05K1/0228 ,  H01F27/2804 ,  H05K1/144 ,  H05K1/18 ,  H01F2027/2809 ,  H05K2201/093 ,  H05K2201/0979 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/10151

Abstract: An anti-interference circuit board and a terminal, where the anti-interference circuit board includes a substrate having a first surface and a first region for placing a magnetometer is disposed on the first surface. A plurality of circuit layers are disposed in the substrate in a stacked manner. The first functional circuit and the second functional circuit are disposed to compensate for interference to the magnetometer in the first region, and during disposing, the first functional circuit and the second functional circuit are located below the magnetometer to reduce an occupied surface area of the anti-interference circuit board.

公开(公告)号：US20230337360A1

公开(公告)日：2023-10-19

申请号：US17724326

申请日：2022-04-19

Applicant: DELL PRODUCTS L.P.

Inventor： Sandor Farkas ,  Mark Smith ,  Bhyrav Mutnury

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/113 ,  H05K1/0215 ,  H05K2201/09481 ,  H05K2201/093

Abstract: A CPU includes a processor die and a substrate. The processor die includes first signal contacts, power contacts, and ground contacts. The processor die is affixed and electrically coupled to the substrate on a first surface of the substrate. The substrate routes the first signal contacts to associated second signal contacts on a second surface of the substrate. The substrate further routes a subset of the power contacts to a power pad on the first surface of the substrate, and routes a subset of the ground contacts to a ground pad on the first surface of the substrate.

公开(公告)号：US11737227B2

公开(公告)日：2023-08-22

申请号：US17677785

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Kemal Aygun

IPC: H05K7/10 ,  H05K1/11 ,  H05K1/02 ,  H01R13/24

CPC classification number: H05K7/1061 ,  H01R13/24 ,  H05K1/0253 ,  H05K1/112 ,  H05K2201/093 ,  H05K2201/09609 ,  H05K2201/10719

Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.

公开(公告)号：US20180279466A1

公开(公告)日：2018-09-27

申请号：US15920508

申请日：2018-03-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： RYOSUKE SHIOZAKI ,  YUTO SUZUKI ,  HIDEKI IWAKI

IPC: H05K1/02 ,  H01P3/08 ,  H05K1/11 ,  H05K3/42 ,  H01Q1/38

CPC classification number: H05K1/0251 ,  H01P3/08 ,  H01P5/028 ,  H01Q1/38 ,  H01Q21/0075 ,  H01Q21/065 ,  H05K1/0242 ,  H05K1/0243 ,  H05K1/0248 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/10098

Abstract: A circuit board includes: a substrate; a first power feed line disposed so as to be close to a plurality of radiating elements provided on a surface of the substrate and to extend in a first direction; a first connection conductor extending in a second direction orthogonal to the first direction, one end of the first connection conductor being connected to the first power feed line substantially at its central portion in the first direction; and a second power feed line that has a first line part extending in a third direction orthogonal to the second direction, the first line part joining to another end of the first connection conductor, and also has a second line part branching from the first line part, the second line part joining to the other end from a third direction side.

公开(公告)号：US20180048045A1

公开(公告)日：2018-02-15

申请号：US15783192

申请日：2017-10-13

Applicant: Sony Semiconductor Solutions Corporation

Inventor： Hidekazu KIKUCHI ,  Takayuki MOGI ,  Yoshiyuki AKIYAMA ,  Hirofumi KAWAMURA

IPC: H01P5/02 ,  H01P3/12 ,  H01P5/107 ,  H01R13/66 ,  H05K1/02 ,  H04B3/56 ,  H04B7/24 ,  H01R24/76 ,  H01R13/6461 ,  H01R103/00 ,  H01R24/28

CPC classification number: H01P5/02 ,  H01P1/208 ,  H01P3/12 ,  H01P3/121 ,  H01P3/165 ,  H01P5/024 ,  H01P5/082 ,  H01P5/087 ,  H01P5/1022 ,  H01P5/107 ,  H01P5/18 ,  H01P5/182 ,  H01P5/188 ,  H01R13/6461 ,  H01R13/665 ,  H01R24/28 ,  H01R24/76 ,  H01R2103/00 ,  H04B3/56 ,  H04B7/24 ,  H05K1/0225 ,  H05K1/0239 ,  H05K2201/093 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09754

Abstract: A signal transmission system including: a first connector apparatus, and a second connector apparatus that is coupled with the first connector apparatus. The first connector apparatus and the second connector apparatus are coupled together to form an electromagnetic field coupling unit, and a transmission object signal is converted into a radio signal, which is then transmitted through the electromagnetic field coupling unit, between the first connector apparatus and the second connector apparatus.

公开(公告)号：US20180014373A1

公开(公告)日：2018-01-11

申请号：US15587567

申请日：2017-05-05

Applicant: Lumileds LLC

Inventor： Zhihua Song ,  Wouter Soer ,  Ron Bonne ,  Yifeng Qiu

IPC: H05B33/08 ,  H05K1/02 ,  H05K3/40 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  H05K3/30 ,  H05K1/05

CPC classification number: H05B33/0845 ,  H01L25/167 ,  H01L25/50 ,  H01R13/6591 ,  H05B33/0809 ,  H05B33/0815 ,  H05B33/0884 ,  H05B33/0887 ,  H05K1/0203 ,  H05K1/0215 ,  H05K1/0224 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/0262 ,  H05K1/053 ,  H05K1/056 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0061 ,  H05K3/107 ,  H05K3/146 ,  H05K3/16 ,  H05K3/181 ,  H05K3/303 ,  H05K3/4076 ,  H05K3/44 ,  H05K3/4608 ,  H05K3/4644 ,  H05K3/465 ,  H05K3/4661 ,  H05K3/467 ,  H05K3/4679 ,  H05K3/4688 ,  H05K9/0084 ,  H05K9/0088 ,  H05K13/00 ,  H05K2201/066 ,  H05K2201/0723 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09563 ,  H05K2201/10106 ,  H05K2201/10166 ,  H05K2201/10522

Abstract: A multi-layer metal core printed circuit board (MCPCB) has mounted on it at least one or more heat-generating LEDs and one or more devices configured to provide current to the one or more LEDs. The one or more devices may include a device that carries a steep slope voltage waveform. Since there is typically a very thin dielectric between the patterned copper layer and the metal substrate, the steep slope voltage waveform may produce a current in the metal substrate due to AC coupling via parasitic capacitance. This AC-coupled current may produce electromagnetic interference (EMI). To reduce the EMI, a local shielding area may be formed between the metal substrate and the device carrying the steep slope voltage waveform. The local shielding area may be conductive and may be electrically connected, to a DC voltage node adjacent to the one or more devices.

公开(公告)号：US20170328392A1

公开(公告)日：2017-11-16

申请号：US15595631

申请日：2017-05-15

Applicant: Kathrein Werke KG

Inventor： Jörg Langenberg ,  Florian Leinenbach ,  Philipp Ponn

IPC: F16B5/00 ,  F16B5/02

CPC classification number: F16B5/0024 ,  F16B5/02 ,  H01Q21/08 ,  H01Q21/26 ,  H05K3/0061 ,  H05K3/3447 ,  H05K9/006 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09072 ,  H05K2201/093 ,  H05K2201/09718 ,  H05K2201/09745 ,  H05K2201/10371 ,  H05K2201/2036

Abstract: What is provided is an adapter plate for HF structures, which is set up for being disposed between a back of a circuit board and a reflector, wherein the adapter plate is electrically conductive, and the adapter plate has an opening or a cavity at every location where an element is passed through the circuit board to the side of the adapter plate, wherein at least one element is passed through the circuit board exclusively for ground contacting.

公开(公告)号：US09767241B2

公开(公告)日：2017-09-19

申请号：US12749254

申请日：2010-03-29

Applicant: Norman L. Rogers ,  John W. Hoffman ,  Jun Feng ,  Charles Krauter

Inventor： Norman L. Rogers ,  John W. Hoffman ,  Jun Feng ,  Charles Krauter

IPC: G06F17/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00

CPC classification number: G06F17/5068 ,  H05K1/0206 ,  H05K1/029 ,  H05K1/0295 ,  H05K1/111 ,  H05K1/114 ,  H05K3/0005 ,  H05K3/0064 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10636 ,  H05K2203/173 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124

Abstract: A method and apparatus for inputting a plurality of different circuit schematics designed with printed circuit board (PCB) mountable components; extracting circuit topologies for said plurality of different circuit schematics; transforming said extracted circuit topologies to a fixed number of connection points; and generating a configurable circuit PCB physical layout pattern having said fixed number of connection points such that said PCB mountable components when positioned on one or more of said fixed number of connection points can implement any circuit represented by said plurality of different circuit schematics.