公开(公告)号：US20070253176A1

公开(公告)日：2007-11-01

申请号：US11797161

申请日：2007-05-01

Applicant: Jun Ishii ,  Yasunari Ooyabu

Inventor： Jun Ishii ,  Yasunari Ooyabu

IPC: H05K7/00

CPC classification number: H05K1/0259 ,  G11B5/484 ,  G11B5/486 ,  H05K1/056 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/09554

Abstract: A wired circuit board has a metal supporting board, an insulating base layer formed on the metal supporting board, a conductive pattern formed on the insulating base layer and including at least one pair of wires arranged in mutually spaced-apart and opposed relation having different potentials, a semiconductive layer formed on the insulating base layer to cover the conductive pattern and electrically connected to the metal supporting board on one side outside a region where the pair of wires are opposed, and an insulating cover layer formed on the semiconductive layer.

Abstract translation: 布线电路板具有金属支撑板，形成在金属支撑板上的绝缘基底层，形成在绝缘基底层上的导电图案，并且包括以相互间隔开和相对关系布置的具有不同电位的至少一对导线 形成在所述绝缘基底层上的半导体层，以覆盖所述导电图案并且在所述一对导线相对的区域的外侧的一侧电连接到所述金属支撑板，以及形成在所述半导体层上的绝缘覆盖层。

公开(公告)号：US07245001B2

公开(公告)日：2007-07-17

申请号：US10915803

申请日：2004-08-11

Applicant: Boyd L. Coomer ,  Michael Walk

Inventor： Boyd L. Coomer ,  Michael Walk

IPC: H01L29/40 ,  H01L21/48

CPC classification number: H01L21/4857 ,  H05K3/107 ,  H05K3/386 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/09554 ,  H05K2203/0315 ,  H05K2203/1142 ,  Y10T29/49126 ,  Y10T29/49128

Abstract: Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.

Abstract translation: 将粘合材料施加到金属芯层的表面。 从金属芯层的导电区域去除粘合材料。 金属接触件设置在金属芯层的导电区域上。 金属芯层层压到压印堆积层上，积层层具有电介质区域和导电区域，其中金属芯层的非导电区域结合到堆积层的电介质区域和金属芯层的导电区域 芯层结合到印迹堆积层的导电区域。

公开(公告)号：US07228623B2

公开(公告)日：2007-06-12

申请号：US10291876

申请日：2002-11-08

Applicant: Kevin C. Olson ,  Alan E. Wang

Inventor： Kevin C. Olson ,  Alan E. Wang

IPC: H01K3/10 ,  B05D1/36 ,  G03C5/00

CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

Abstract translation: 提供了用于制造多层电路组件的工艺和通过这些工艺制造的多层电路组件。 该方法包括（a）提供基底，其至少一个区域包括多个通孔，这些区域的通孔密度为500至10,000个孔/平方英寸（75至1550个孔/平方厘米）; （b）将介电涂层施加到所述基底的所有暴露表面上以在其上形成保形涂层; 和（c）在基片的所有表面上涂一层金属。 可以包括诸如电路化的附加处理步骤。

公开(公告)号：US20070012751A1

公开(公告)日：2007-01-18

申请号：US11180188

申请日：2005-07-13

Applicant: John Waldvogel ,  Herman Miller

Inventor： John Waldvogel ,  Herman Miller

IPC: B23K31/02 ,  B23K35/12

CPC classification number: B23K1/0016 ,  B23K2101/36 ,  H05K1/0206 ,  H05K1/0271 ,  H05K3/0061 ,  H05K3/305 ,  H05K3/341 ,  H05K3/386 ,  H05K2201/0305 ,  H05K2201/09318 ,  H05K2201/09554 ,  H05K2201/10022 ,  H05K2201/10636 ,  H05K2201/10969 ,  H05K2203/0455 ,  Y02P70/611

Abstract: An electrical circuit apparatus (300) that includes; a substrate (330) having a top side, a ground layer (336), at least one thermal aperture (332), and at least one solder aperture (334); a heat sink (310); and an adhesive layer (320) for mechanically coupling the heat sink to the ground layer of the substrate, the adhesive layer having at least one aperture (322) wherein aligning the at least one substrate solder aperture with the at least one adhesive layer aperture enables solder wetting in a predetermined area between the heat sink and the ground layer of the substrate.

Abstract translation: 一种电路装置（300），包括： 具有顶侧的衬底（330），接地层（336），至少一个热孔（332）和至少一个焊接孔（334）; 散热器（310）; 以及用于将散热器机械地耦合到衬底的接地层的粘合剂层（320），所述粘合剂层具有至少一个孔（322），其中使所述至少一个衬底焊接孔与所述至少一个粘合剂层孔径对准使得能够 在散热器和衬底的接地层之间的预定区域中的焊料润湿。

公开(公告)号：US07159308B2

公开(公告)日：2007-01-09

申请号：US11224197

申请日：2005-09-12

Applicant: Alan E. Wang ,  Kevin C. Olson ,  Thomas H. Di Stefano

Inventor： Alan E. Wang ,  Kevin C. Olson ,  Thomas H. Di Stefano

IPC: H05K3/36

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/44 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09554 ,  H05K2201/10446 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: Provided is a method of forming a circuit board including (a) providing a first conductive sheet; (b) selectively removing one or more portions of the first conductive sheet to form a first panel having a first circuit board that is coupled to a disposable part of the first panel by at least one tab that extends from an edge of the first circuit board to an edge of the disposable part of the first panel; (c) applying an insulating coating to the first circuit board so that at least each edge of the first circuit board is covered thereby; and (d) separating the first circuit board from the disposable part in a manner whereupon at least part of the tab remains attached to the first circuit board and includes an exposed edge of the conductive sheet of the first circuit board. Circuit boards formed by the method are also provided.

Abstract translation: 提供一种形成电路板的方法，包括：（a）提供第一导电片; （b）选择性地去除所述第一导电片的一个或多个部分以形成具有第一电路板的第一面板，所述第一电路板通过从所述第一电路板的边缘延伸的至少一个接片连接到所述第一面板的一次性部分 到所述第一面板的一次性部分的边缘; （c）向第一电路板施加绝缘涂层，使得第一电路板的至少每个边缘被覆盖; 和（d）以一种方式将第一电路板与一次性部分分离，由此至少部分突片保持附接到第一电路板并且包括第一电路板的导电片的暴露边缘。 还提供了通过该方法形成的电路板。

公开(公告)号：US07145231B2

公开(公告)日：2006-12-05

申请号：US10844392

申请日：2004-05-13

Applicant: Takehiko Hasebe ,  Takehide Yokozuka ,  Nobuyuki Ushifusa ,  Masahide Harada ,  Eiji Matsuzaki ,  Hiroshi Hozoji

Inventor： Takehiko Hasebe ,  Takehide Yokozuka ,  Nobuyuki Ushifusa ,  Masahide Harada ,  Eiji Matsuzaki ,  Hiroshi Hozoji

IPC: H01L23/34

CPC classification number: H01L24/16 ,  H01L23/142 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/32057 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/83851 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01054 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/021 ,  H05K1/056 ,  H05K1/144 ,  H05K3/384 ,  H05K3/4608 ,  H05K3/4641 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10734 ,  H01L2924/05432 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides an electronic apparatus having a metal core substrate including a metal plate, an insulating layer formed on the metal plate and a conductive layer formed on the insulating layer, and an electronic part, and to which the conductive layer and a terminal of the electronic part are connected. In the electronic apparatus, a member having a high thermal conductivity is arranged so as to be in contact with both of the metal plate and the electronic part. Accordingly, a heat radiating property of the electronic apparatus is increased.

公开(公告)号：US20060159898A1

公开(公告)日：2006-07-20

申请号：US11329223

申请日：2006-01-11

Applicant: Hisae Uchiyama ,  Naotaka Kinjou ,  Takashi Kondou ,  Takahiro Fukuoka ,  Jun Ishii

Inventor： Hisae Uchiyama ,  Naotaka Kinjou ,  Takashi Kondou ,  Takahiro Fukuoka ,  Jun Ishii

IPC: C08F8/00 ,  B32B3/00

CPC classification number: H05K1/0259 ,  C08L79/08 ,  H05K1/056 ,  H05K1/167 ,  H05K2201/0154 ,  H05K2201/09554 ,  Y10T428/24917

Abstract: To provide a semi-conducting resin composition capable of forming a semi-conducting layer which exhibits a less variable surface resistivity even when subjected to ultrasonic cleaning and effectively discharges static electricity and also provide a wired circuit board comprising the semi-conducting layer composed of the semi-conducting resin composition, an imide resin or a precursor of an imide resin and conducting particles are mixed in a solvent so that the semi-conducting resin composition containing the imide resin or imide resin precursor dissolved therein and the conducting particles dispersed therein is prepared. Then, the semi-conducting resin composition is coated on a surface of an insulating cover layer (5) including the terminal portion (6) of a suspension board with circuit (1) and dried to form a semi-conducting layer (7). Thereafter, the semi-conducting layer 7 formed in the terminal portion (6) is removed by etching.

Abstract translation: 为了提供能够形成半导体层的半导体树脂组合物，即使经受超声波清洗并且有效地排出静电也表现出较小的表面电阻率，并且还提供一种布线电路板，该布线电路板包括由 半导体树脂组合物，酰亚胺树脂或酰亚胺树脂的前体和导电颗粒在溶剂中混合，使得其中含有酰亚胺树脂或酰亚胺树脂前体溶解的半导体树脂组合物和分散在其中的导电颗粒被制备 。 然后，将半导体树脂组合物涂布在包括具有电路（1）的悬挂板的端子部分（6）的绝缘覆盖层（5）的表面上并干燥以形成半导电层（7）。 此后，通过蚀刻去除形成在端子部分（6）中的半导电层7。

公开(公告)号：US07063249B2

公开(公告)日：2006-06-20

申请号：US11000697

申请日：2004-12-01

Applicant: John M. Waldvogel ,  Brian R. Bielick ,  Herman J. Miller ,  Billy J. Van Cannon

Inventor： John M. Waldvogel ,  Brian R. Bielick ,  Herman J. Miller ,  Billy J. Van Cannon

IPC: B23K31/00

CPC classification number: H05K1/021 ,  H05K1/182 ,  H05K3/0061 ,  H05K3/341 ,  H05K3/386 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/09554 ,  H05K2201/10166 ,  H05K2201/10969 ,  H05K2203/042 ,  H05K2203/063

Abstract: An electrical circuit apparatus (300) that includes: a substrate (330) having a ground layer (336), at least one device aperture (332), and at least one solder aperture (334); a heat sink (310); and an adhesive layer (320) for mechanically coupling the heat sink to the ground layer of the substrate such that at least a portion of the substrate device aperture overlaps the heat sink, the adhesive layer having at least one device aperture and at least one solder aperture, wherein aligning the at least one substrate solder aperture with the at least one adhesive layer solder aperture and aligning the at least one substrate device aperture with the at least one adhesive layer device aperture enables solder wetting in a predetermined area between the heat sink and the ground layer of the substrate.

Abstract translation: 一种电路设备（300），包括：具有接地层（336），至少一个器件孔（332）和至少一个焊料孔（334）的衬底（330）; 散热器（310）; 以及用于将所述散热器机械耦合到所述基板的接地层的粘合剂层（320），使得所述基板装置孔的至少一部分与所述散热器重叠，所述粘合剂层具有至少一个装置孔和至少一个焊料 孔，其中将所述至少一个衬底焊接孔与所述至少一个粘合剂层焊接孔对准并且将所述至少一个衬底器件孔与所述至少一个粘合剂层器件孔对准使得焊料在所述散热器和所述散热器之间的预定区域中润湿 衬底的接地层。

公开(公告)号：US20060005995A1

公开(公告)日：2006-01-12

申请号：US11224197

申请日：2005-09-12

Applicant: Alan Wang ,  Kevin Olson ,  Thomas Di Stefano

Inventor： Alan Wang ,  Kevin Olson ,  Thomas Di Stefano

IPC: H05K1/03

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/44 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09554 ,  H05K2201/10446 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: Provided is a method of forming a circuit board including (a) providing a first conductive sheet; (b) selectively removing one or more portions of the first conductive sheet to form a first panel having a first circuit board that is coupled to a disposable part of the first panel by at least one tab that extends from an edge of the first circuit board to an edge of the disposable part of the first panel; (c) applying an insulating coating to the first circuit board so that at least each edge of the first circuit board is covered thereby; and (d) separating the first circuit board from the disposable part in a manner whereupon at least part of the tab remains attached to the first circuit board and includes an exposed edge of the conductive sheet of the first circuit board. Circuit boards formed by the method are also provided.

Abstract translation: 提供一种形成电路板的方法，包括：（a）提供第一导电片; （b）选择性地去除所述第一导电片的一个或多个部分以形成具有第一电路板的第一面板，所述第一电路板通过从所述第一电路板的边缘延伸的至少一个接片连接到所述第一面板的一次性部分 到所述第一面板的一次性部分的边缘; （c）向第一电路板施加绝缘涂层，使得第一电路板的至少每个边缘被覆盖; 以及（d）以一种方式将第一电路板与一次性部分分开，由此至少部分突片保持附接到第一电路板并且包括第一电路板的导电片的暴露边缘。 还提供了通过该方法形成的电路板。

公开(公告)号：US20050280944A1

公开(公告)日：2005-12-22

申请号：US10870082

申请日：2004-06-16

Applicant: Chao-Hui Yang ,  Yen Fu ,  Li-Yan Zhu ,  Manny Hernandez ,  Ellis Cha ,  Yong Luo

Inventor： Chao-Hui Yang ,  Yen Fu ,  Li-Yan Zhu ,  Manny Hernandez ,  Ellis Cha ,  Yong Luo

IPC: G11B5/48 ,  G11B21/16 ,  G11B21/20 ,  H05K1/02 ,  H05K1/05 ,  H05K3/46

CPC classification number: G11B5/486 ,  G11B5/484 ,  H05K1/0228 ,  H05K1/056 ,  H05K3/4685 ,  H05K2201/09554 ,  H05K2201/0969 ,  H05K2201/097

Abstract: An externally wireless laminated suspension for a hard disk drive are disclosed. In one embodiment, the externally wireless laminated suspension has an insulating layer to electrically isolate a first and second electrical trace from a conductive support layer. The second electrical trace crosses over the first electrical trace. The first electrical trace may be made of a first part on one side of the second electrical trace and a second part on the opposite side of the electrical trace. A conductive island area may be patterned into the support layer. The conductive island area may electrically couple the first part of the first electrical trace to the second part. The number of crossover points that the first electrical trace has may equal the number of crossover points that the second electrical trace has.

Abstract translation: 公开了一种用于硬盘驱动器的外部无线层叠悬架。 在一个实施例中，外部无线层叠悬架具有绝缘层，以将第一和第二电迹线与导电支撑层电隔离。 第二电迹线穿过第一电迹线。 第一电迹线可以由第二电迹线的一侧上的第一部分和在电迹线的相对侧上的第二部分制成。 导电岛区域可以被图案化成支撑层。 导电岛区域可以将第一电迹线的第一部分电耦合到第二部分。 第一电迹线具有的交叉点的数量可以等于第二电迹线具有的交叉点的数量。