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    RESONANT SENSOR AND AN ASSOCIATED SENSING METHOD
    171.
    发明申请
    RESONANT SENSOR AND AN ASSOCIATED SENSING METHOD 有权
    谐振传感器和相关感测方法

    公开(公告)号：US20160290944A1

    公开(公告)日：2016-10-06

    申请号：US15175127

    申请日：2016-06-07

    Applicant: General Electric Company

    Inventor： Radislav Alexandrovich Potyrailo ,  Yongjae Lee

    IPC: G01N27/02

    CPC classification number: G01N33/0031 ,  G01N27/026 ,  H05K1/16 ,  H05K2201/0338 ,  H05K2201/09263 ,  H05K2201/10151 ,  Y10T29/4913

    Abstract: A sensing system for selective analyte detection in presence of interferences is presented. The sensing system includes an inductor-capacitor-resistor (LCR) resonant sensor includes a substrate, a plurality of first sensing elements mutually spaced apart and disposed on the substrate, a plurality of second sensing elements, each second sensing element disposed overlapping a corresponding first sensing element of the plurality of second sensing elements, and a protecting film applied onto the plurality of first sensing elements and the plurality of second sensing elements, wherein the protecting film is disposed to be in a physical contact with the analyte and is configured to enable an operational contact of the plurality of first sensing elements and the plurality of second sensing elements with the analyte.

    Abstract translation: 提出了一种用于在存在干扰的情况下选择性分析物检测的感测系统。 感测系统包括电感器 - 电容电阻（LCR）谐振传感器，其包括衬底，相互间隔开并设置在衬底上的多个第一感测元件，多个第二感测元件，每个第二感测元件与相应的第一 多个第二感测元件的感测元件以及施加到所述多个第一感测元件和所述多个第二感测元件上的保护膜，其中所述保护膜设置成与所述分析物物理接触，并且被配置为使得能够 多个第一感测元件和多个第二感测元件与分析物的操作接触。

    Making multi-layer micro-wire structure
    175.
    发明授权
    Making multi-layer micro-wire structure 有权
    制作多层微线结构

    公开(公告)号：US09345144B2

    公开(公告)日：2016-05-17

    申请号：US13863615

    申请日：2013-04-16

    Applicant: Eastman Kodak Company

    Inventor： Ronald Steven Cok

    IPC: H05K1/09 ,  H05K3/40 ,  H01L21/288 ,  H05K3/12 ,  G06F3/044

    CPC classification number: H05K3/1258 ,  G06F3/044 ,  G06F2203/04103 ,  H01L21/288 ,  H05K1/092 ,  H05K3/4053 ,  H05K2201/0338 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/0139 ,  H05K2203/1476 ,  H05K2203/1581

    Abstract: A method of making a multi-layer micro-wire structure includes providing a substrate with a plurality of micro-channels. First and second material compositions are provided. The first material composition is coated over the substrate and micro-channels and then removed from the substrate surface but not the micro-channels. The second material composition is coated over the substrate, in the micro-channels, and over the first materials, and then removed from the substrate surface but not the micro-channels. The first and second material compositions are cured in the micro-channels in a common step to form a cured first material layer and a cured second material layer in the micro-channels. The cured first material layer and the cured second material layer form an electrically conductive multi-layer micro-wire in each micro-channel.

    Abstract translation: 制造多层微线结构的方法包括提供具有多个微通道的衬底。 提供了第一和第二材料组合物。 将第一材料组合物涂覆在基材和微通道上，然后从基材表面除去而不是微通道。 第二材料组合物涂覆在基底上，在微通道中，并在第一材料上，然后从基底表面而不是微通道上移除。 第一和第二材料组合物在微通道中以常规步骤固化，以在微通道中形成固化的第一材料层和固化的第二材料层。 固化的第一材料层和固化的第二材料层在每个微通道中形成导电多层微线。

    WIRING BOARD
    176.
    发明申请
    WIRING BOARD 审中-公开
    接线板

    公开(公告)号：US20160128183A1

    公开(公告)日：2016-05-05

    申请号：US14918618

    申请日：2015-10-21

    Applicant: KYOCERA Circuit Solutions, Inc.

    Inventor： Keisaku MATSUMOTO

    IPC: H05K1/02

    CPC classification number: H05K1/0224 ,  H05K3/243 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/0347

    Abstract: The wiring board of the present invention includes an insulating layer, a strip-shaped wiring conductor for signals disposed on a main surface of the insulating layer, and a plain conductor for grounding or power disposed on the main surface of the insulating layer; and the thickness of the plane conductor is larger than the thickness of the strip-shaped wiring conductor. In the wiring board of the present invention, the thickness of the plane conductor is preferably 1 to 15 μm larger than the thickness of the strip-shaped wiring conductor. The strip-shaped wiring conductor has a thickness of preferably 3 to 10 μm, and the plane conductor has a thickness of preferably 5 to 15 μm.

    Abstract translation: 本发明的布线基板包括绝缘层，用于设置在绝缘层的主表面上的信号的带状布线导体和布置在绝缘层的主表面上的用于接地或电力的扁平导体; 并且平面导体的厚度大于带状布线导体的厚度。 在本发明的布线基板中，平面导体的厚度优选比带状布线导体的厚度大1〜15μm。 带状布线导体的厚度优选为3〜10μm，平面导体的厚度优选为5〜15μm。

    Method for producing conductive tracks
    177.
    发明授权
    Method for producing conductive tracks 有权
    导电轨道的制造方法

    公开(公告)号：US09332648B2

    公开(公告)日：2016-05-03

    申请号：US14403922

    申请日：2013-02-14

    Applicant: RMT Limited

    Inventor： Vasiliy Sergeevich Anosov ,  Vasiliy Vasilevich Volodin ,  Gennadiy Gyusamovich Gromov ,  Elena Vladmirovna Mazikina ,  Aleksandr Aleksandrovich Nazarenko ,  Sergey Sergeevich Ryabov

    IPC: H05K3/02 ,  H05K3/06 ,  H05K3/24 ,  H01L23/498 ,  H01L21/48 ,  H05K1/03

    CPC classification number: H05K3/065 ,  H01L21/4846 ,  H01L23/498 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2203/107 ,  Y10T29/49156 ,  H01L2924/00

    Abstract: The method for producing conductive tracks includes applying continuous metallization layers to a non-conductive substrate, forming a metallization pattern, and applying to the formed tracks a protective barrier layer and a layer for soldering and/or welding elements of parts to the conductive tracks. The continuous metallization layers are applied by consecutively applying an adhesive layer, a conductive layer, and a metal layer, acting as a mask, to the non-conductive substrate. To form the metallization pattern, a mask is formed by laser ablation on sections of the metal layer not occupied by conductive tracks, then selective chemical etching removes the conductive layer and adhesive sublayer from the exposed sections, and selective chemical etching removes the mask, after which the protective barrier layer and layer for soldering and/or welding are applied.

    Abstract translation: 用于制造导电迹线的方法包括将连续的金属化层施加到非导电基底上，形成金属化图案，以及向形成的轨道施加保护性阻挡层和用于将元件的元件焊接和/或焊接到导电迹线的层。 连续金属化层通过连续施加作为掩模的粘合剂层，导电层和金属层施加到非导电基材上。 为了形成金属化图案，在未被导电轨迹占据的金属层的部分上通过激光烧蚀形成掩模，然后选择性化学蚀刻从暴露部分去除导电层和粘合剂子层，并且选择性化学蚀刻除去掩模 其中施加用于焊接和/或焊接的保护屏障层和层。

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