公开(公告)号：US5419807A

公开(公告)日：1995-05-30

申请号：US223642

申请日：1994-04-06

Applicant: Salman Akram ,  Warren M. Farnworth

Inventor： Salman Akram ,  Warren M. Farnworth

IPC: G01R1/067 ,  G01R1/073 ,  H01L21/768 ,  H01L23/13 ,  H05K1/03 ,  H05K3/04 ,  H05K3/06 ,  H05K3/32 ,  H05K3/40 ,  H01L21/306

CPC classification number: H01L23/13 ,  G01R1/06711 ,  G01R1/07314 ,  H01L21/76895 ,  G01R1/06738 ,  G01R3/00 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  H05K3/048 ,  H05K3/064 ,  H05K3/325 ,  H05K3/4007

Abstract: A method is disclosed of forming a high elevation area and a low elevation area in a substrate and of electrically interconnecting the high elevation area and the low elevation area. The method includes anisotropically etching into a non-masked portion of monocrystalline silicon in a selective manner of one silicon plane relative to another silicon plane to produce a high elevation area and a low elevation area which are laterally angled relative to one another. The high elevation area and the low elevation area thereby interconnected by a substantially planar, non-perpendicularly angled surface. Such areas and plane are then doped to form a continuous electrically conductive and interconnecting diffusion region extending from the high elevation area, through and along the angled surface to the low elevation area. A semiconductor apparatus having the above construction is also disclosed. Also disclosed is an epitaxial silicon growth and etching process, and a semiconductor apparatus having multiple different monocrystalline silicon portions. Further disclosed is a method of producing a testing apparatus having a projection formed essentially of electrically conductive polysilicon.

Abstract translation: 公开了一种在衬底中形成高仰角区域和低仰角区域并将高高度区域和低仰角区域电连接的方法。 该方法包括以相对于另一硅平面的一个硅平面的选择性方式各向异性蚀刻成单晶硅的非掩模部分，以产生相对于彼此横向成角度的高仰角区域和低仰角区域。 因此，高仰角区域和低仰角区域通过基本上平面的非垂直成角度的表面相互连接。 然后将这样的区域和平面掺杂以形成从高仰角区域延伸穿过且沿着倾斜表面延伸到低仰角区域的连续的导电和互连扩散区域。 还公开了具有上述结构的半导体装置。 还公开了外延硅生长和蚀刻工艺，以及具有多个不同单晶硅部分的半导体器件。 还公开了一种制造具有基本上由导电多晶硅形成的突起的测试装置的方法。

公开(公告)号：US5410449A

公开(公告)日：1995-04-25

申请号：US261320

申请日：1994-06-16

Applicant: Kevin W. Brunner

Inventor： Kevin W. Brunner

IPC: H01L21/60 ,  H01L23/498 ,  H01L25/16 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K7/20

CPC classification number: H05K3/341 ,  H01L23/49838 ,  H01L24/81 ,  H01L25/16 ,  H05K1/111 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K1/0201 ,  H05K1/0203 ,  H05K1/0306 ,  H05K2201/0373 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10166 ,  H05K2201/10689 ,  H05K2201/10969 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613

Abstract: A method is provided for improving the integrity of a solder joint between a large surface-mounted integrated circuit component and a circuit board substrate. In particular, the strength of the solder joint is promoted by preventing the formation of voids in the solder joint during a reflow soldering process by which the component is secured to the circuit board. The method relies on the geometry of the conductor pad used to provide electrical contact between the component and the remaining circuitry and thermal contact between the component and the substrate. The conductor pad is composed of a number of platforms which are defined by a network of trenches that provides numerous passages through which the solder and flux gases may flow during the soldering process. The platforms serve as sites on which the solder compound can be selectively deposited in a manner that further enhances the soldering process, such that voids within the solder joint are substantially avoided.

Abstract translation: 提供了一种用于提高大型表面安装集成电路部件和电路板基板之间的焊接接头的完整性的方法。 特别地，通过在回流焊接过程中防止在焊接接头中形成空隙来促进焊点的强度，通过该焊接过程，部件被固定到电路板。 该方法依赖于用于提供部件与剩余电路之间的电接触的导体焊盘的几何形状以及部件和基板之间的热接触。 导体焊盘由许多平台构成，这些平台由沟槽网络限定，其提供了许多通道，通过焊接和焊剂气体可以在焊接过程期间流过。 这些平台作为可以以进一步增强焊接工艺的方式选择性地沉积焊料化合物的位置，使得基本上避免了焊点内的空隙。

公开(公告)号：US5373113A

公开(公告)日：1994-12-13

申请号：US53699

申请日：1993-04-29

Applicant: Hideki Ishii

Inventor： Hideki Ishii

IPC: B23K1/00 ,  B23K1/20 ,  H05K1/11 ,  H05K3/24 ,  H05K3/34 ,  H05K1/02

CPC classification number: H05K3/3452 ,  B23K1/0016 ,  B23K1/20 ,  H05K3/3405 ,  H05K3/3463 ,  H05K1/117 ,  H05K2201/0373 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/099 ,  H05K2203/043 ,  H05K2203/047

Abstract: A process for reflow mounting an electronic component includes coating a terminal electrode on a mounting board with a second solder having a second melting point higher than a reflow temperature, placing the mounting board with the electronic component on a mounting land on a conveyor which may be brought into contact with the second solder on the terminal electrode, and heating the mounting board to the reflow temperature. The terminal electrode may be coated with a solder repelling material at a selected dividing area effective for dividing the terminal electrode into a plurality of sections substantially isolated from each other in terms of solder flow. Alternatively, a mounting jig may be used for supporting the mounting board without bringing the second solder on the terminal electrode into contact with the mounting jig.

Abstract translation: 一种用于回流焊安装电子部件的工艺包括：在具有第二熔点高于回流温度的第二焊料的安装板上涂覆端子电极，将具有电子部件的安装板放置在可以是 与端子电极上的第二焊料接触，并将安装板加热到回流温度。 端子电极可以在选择的分割区域涂覆有排斥材料，其有效地将端子电极分成在焊料流动方面彼此基本隔离的多个部分。 或者，可以使用安装夹具来支撑安装板，而不使端子电极上的第二焊料与安装夹具接触。

公开(公告)号：US5346117A

公开(公告)日：1994-09-13

申请号：US97604

申请日：1993-07-27

Applicant: Harold Kohn ,  Donald J. Lazzarini

Inventor： Harold Kohn ,  Donald J. Lazzarini

IPC: G06F13/40 ,  H05K1/00 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46 ,  H05K3/36

CPC classification number: H05K3/4635 ,  G06F13/409 ,  H05K3/462 ,  H05K1/0393 ,  H05K2201/0305 ,  H05K2201/0373 ,  H05K2201/09536 ,  H05K2201/09572 ,  H05K2201/096 ,  H05K2201/10159 ,  H05K3/328 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  Y10T29/49126

Abstract: Disclosed is a method for manufacturing a stacked circuitized flex structure. The structure is a laminate for Z-axis communication within a parallel processor. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Z-axis circuitization is carried out by providing vias and through holes in individual circuitized flex strips. These vias and through holes are circuited and plated. This is followed by filling the vias and through holes with solder and forming solder bumps at the tops and bottoms of the vias and through holes. A sticker sheet with clearance holes for the solder bumps is provided, and a plurality of the circuitized flex strips are laid up for lamination to form a stack of circuitized flexible strips. Lamination is carried out at elevated pressure and temperature to crush the solder bumps, bond, and homogenize solder bump material and fuse the sticker sheets. Next, the stack is cooled to solidify the homogenized solder bump material.

Abstract translation: 公开了一种用于制造堆叠电路化柔性结构的方法。 该结构是在并行处理器内用于Z轴通信的层压板。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 通过在单独的电路化柔性条中设置通孔和通孔来进行Z轴电路化。 这些通孔和通孔被循环和电镀。 然后在通孔和通孔的顶部和底部填充通孔和通孔用焊料和形成焊料凸块。 提供了具有用于焊料凸块的间隙孔的贴纸，并且堆叠多个电路化的柔性条以层压以形成电路化的柔性条的堆叠。 层压在升高的压力和温度下进行，以粉碎焊料凸块，粘合和均质焊料凸块材料并熔合贴纸。 接下来，将堆叠冷却以固化均质化的焊料凸块材料。

公开(公告)号：US4950843A

公开(公告)日：1990-08-21

申请号：US275836

申请日：1988-11-25

Applicant: Yukitsugu Hirota

Inventor： Yukitsugu Hirota

IPC: H01L21/52 ,  H01L21/60 ,  H01L23/14 ,  H01L23/492 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34

CPC classification number: H01L24/32 ,  H01L23/142 ,  H01L23/492 ,  H01L24/83 ,  H05K1/111 ,  H05K3/341 ,  H01L2224/27013 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/83051 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K1/0203 ,  H05K2201/0373 ,  H05K2201/09781 ,  H05K2201/10166 ,  H05K2201/10969 ,  Y02P70/611 ,  Y02P70/613

Abstract: A mounting structure for a semiconductor device which is mounted onto a metallic wiring layer formed on a surface portion of a metal printed circuit board, in which bonding portions defined by substantially square etched holes are formed in a portion of the metallic wiring layer contacting a bonding material interposed between the metallic wiring layer and the body of the semiconductor device.

Abstract translation: 一种半导体器件的安装结构，其安装在形成在金属印刷电路板的表面部分上的金属布线层上，其中，在金属布线层的与接合 夹在金属布线层和半导体器件本体之间的材料。

公开(公告)号：US4705205A

公开(公告)日：1987-11-10

申请号：US610077

申请日：1984-05-14

Applicant: Leslie J. Allen ,  Gabe Cherian ,  Stephen H. Diaz

Inventor： Leslie J. Allen ,  Gabe Cherian ,  Stephen H. Diaz

IPC: B23K3/06 ,  B23K35/02 ,  H05K3/32 ,  H05K3/34 ,  H05K3/40 ,  H05K13/04 ,  H01L21/60 ,  H01L21/58

CPC classification number: B23K35/0222 ,  B23K3/06 ,  H05K13/0465 ,  H05K3/325 ,  H05K3/3436 ,  H01L2924/00013 ,  H01L2924/0002 ,  H05K2201/0215 ,  H05K2201/0314 ,  H05K2201/0373 ,  H05K2201/1028 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10727 ,  H05K2201/10946 ,  H05K2203/0415 ,  H05K2203/0769 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/4015 ,  Y02P70/613

Abstract: A chip carrier mounting device which is hereinafter also referred to as an "interconnection preform placement device" includes a retaining member having a predetermined pattern of apertures in which are positioned preforms of joint-forming material such as solder. The preform retains its general configuration after the interconnection or soldering process to form a resilient joint which is more capable of withstanding stress, strain and fatique. A method of forming resilient interconnections comprises placing the interconnection retaining member device between parallel patterns of electrically conductive elements, such as the conductive pads on an electronic component and a circuit board, and effecting the bonding of the conductive elements with the preforms. The joint-forming material may be a filled solder composition or a supported solder which substantially maintain their physical shape when the solder is molten, or a conductive elastomer.

Abstract translation: 在下文中也称为“互连预成型件放置装置”的芯片载体安装装置包括具有预定图案的孔的保持构件，其中定位有诸如焊料的接合形成材料的预成型件。 预成型件在互连或焊接工艺之后保持其一般配置，以形成更能承受应力，应变和疲劳的弹性接头。 形成弹性互连的方法包括将互连保持构件装置放置在导电元件的平行图案之间，例如电子元件和电路板上的导电垫，并且实现导电元件与预成型件的结合。 接合形成材料可以是填充的焊料组合物或当焊料熔融时基本保持其物理形状的支撑焊料或导电弹性体。

公开(公告)号：US3851223A

公开(公告)日：1974-11-26

申请号：US30846572

申请日：1972-11-21

Applicant: NIPPON ELECTRIC CO

Inventor： YONEZUKA M ,  MURATA H

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K1/111 ,  H01L2224/83385 ,  H05K1/0306 ,  H05K3/341 ,  H05K3/3452 ,  H05K2201/0373 ,  H05K2201/10969 ,  H05K2201/2081 ,  H05K2203/044 ,  Y02P70/611 ,  Y02P70/613

Abstract: A microcircuit board for use with integrated circuits includes at least one thin film land to which components are to be soldered. The land is divided into solderable and nonsolderable areas, and the amount of solder that is preliminarily applied to the land will be determined by the ratio of the solderable areas to the non-solderable areas.

Abstract translation: 与集成电路一起使用的微电路板包括至少一个要焊接组件的薄膜焊盘。 土地分为可焊接和不可焊接区域，预先施加在焊盘上的焊料量将由可焊接区域与不可焊接区域的比例决定。

公开(公告)号：US3484935A

公开(公告)日：1969-12-23

申请号：US3484935D

申请日：1965-07-28

Applicant: WESTERN ELECTRIC CO

Inventor： BURNS JOHN A

IPC: H01R4/10 ,  H01R12/58 ,  H05K3/40 ,  H05K13/04 ,  H05K3/30 ,  H01R9/00

CPC classification number: H05K3/4046 ,  H01R4/10 ,  H05K13/0417 ,  H05K2201/0133 ,  H05K2201/0373 ,  H05K2201/10295 ,  Y10T29/49147 ,  Y10T29/4987 ,  Y10T29/49872 ,  Y10T29/49915 ,  Y10T29/49943 ,  Y10T29/53174 ,  Y10T29/53657 ,  Y10T29/53709

公开(公告)号：US3187426A

公开(公告)日：1965-06-08

申请号：US18068562

申请日：1962-03-19

Applicant: SPERRY RAND CORP

Inventor： PROHOFSKY LE ROY A

IPC: H01R12/51 ,  H05K3/34 ,  H05K3/36 ,  H05K3/46

CPC classification number: H05K3/368 ,  H01R12/523 ,  H05K3/3447 ,  H05K3/3468 ,  H05K3/4611 ,  H05K2201/0373 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10287 ,  H05K2201/10295 ,  H05K2201/10303 ,  Y10T29/49165

公开(公告)号：US1954403A

公开(公告)日：1934-04-10

申请号：US45570830

申请日：1930-05-26

Applicant: DALY JOHN A

Inventor： DALY JOHN A

IPC: B21D39/03 ,  B23P15/00 ,  H05K3/38

CPC classification number: B23P15/00 ,  B21D39/03 ,  H05K3/383 ,  H05K2201/0355 ,  H05K2201/0373