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    CIRCUIT BOARD STRUCTURE WITH SELECTIVELY CORRESPONDING GROUND LAYERS
    182.
    发明申请
    CIRCUIT BOARD STRUCTURE WITH SELECTIVELY CORRESPONDING GROUND LAYERS 有权

    公开(公告)号：US20170325331A1

    公开(公告)日：2017-11-09

    申请号：US15450204

    申请日：2017-03-06

    Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.

    Inventor： CHIH-HENG CHUO ,  KUO-FU SU ,  GWUN-JIN LIN

    IPC: H05K1/02 ,  H05K1/03

    CPC classification number: H05K1/0245 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0224 ,  H05K1/024 ,  H05K1/0253 ,  H05K1/032 ,  H05K2201/09336

    Abstract: A circuit board structure with selectively corresponding ground layers includes a first ground layer, a second ground layer, and a dielectric layer arranged between the first ground layer and the second ground layer to define a ground layer height difference between the first ground layer and the second ground layer. The first ground layer includes a plurality of non-electromagnetic shield areas. The circuit board includes a plurality of conductor wires formed thereon and selectively classified and divided into a first group of conductor wires and the second group of conductor wires. The first-group conductor wires are arranged to correspond to and electromagnetically couple to the first ground layer, and the second-group conductor wires are arranged to correspond to and electromagnetically couple to the second ground layer through the non-electromagnetic shield areas respectively, so that impedance value control is achieved.

    High speed plug connector having improved high frequency performance
    187.
    发明授权
    High speed plug connector having improved high frequency performance 有权
    具有改进的高频性能的高速插头连接器

    公开(公告)号：US09306334B2

    公开(公告)日：2016-04-05

    申请号：US14287573

    申请日：2014-05-27

    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.

    Inventor： Jian-Jun Zhu ,  Jerry Wu

    IPC: H01R3/00 ,  H01R13/6471 ,  H05K1/02 ,  H01R9/03 ,  H01R13/6585 ,  H05K1/11

    CPC classification number: H01R13/6471 ,  H01R9/034 ,  H01R13/6585 ,  H05K1/0219 ,  H05K1/0245 ,  H05K1/117 ,  H05K2201/09336 ,  H05K2201/09409 ,  H05K2201/10356

    Abstract: A plug connector (100) includes a shell (10) and a printed circuit board (20) received in the shell. The printed circuit board includes a grounding layer (22), a conductive layer (21) disposed at a first side of the grounding layer, and an insulative layer (23) disposed therebetween. The conductive layer includes a pair of grounding traces (210), and a signal channel disposed between and isolated with the grounding traces. The signal channel includes a signal mating portion (221) disposed at a front portion. Each of the grounding traces includes a grounding mating portion (211) disposed at a front portion. Each of the grounding mating portions has a front end extending beyond the signal mating portion. The printed circuit board includes a pair of connecting traces (214). Each of the front ends of the grounding mating portions directly connects with the grounding layer by corresponding one of the connecting traces.

    Abstract translation: 插头连接器（100）包括壳体（10）和容纳在外壳中的印刷电路板（20）。 印刷电路板包括接地层（22），设置在接地层的第一侧的导电层（21）和设置在其间的绝缘层（23）。 导电层包括一对接地迹线（210），以及设置在接地迹线之间并与接地迹线隔离的信号通道。 信号通道包括设置在前部的信号配合部分（221）。 每个接地迹线包括设置在前部的接地配合部分（211）。 每个接地配合部分具有延伸超过信号配合部分的前端。 印刷电路板包括一对连接迹线（214）。 接地配合部分的每个前端通过相应的一个连接迹线与接地层直接连接。

    Circuit layout structure, circuit board and electronic assembly
    188.
    发明授权
    Circuit layout structure, circuit board and electronic assembly 有权
    电路布局结构，电路板和电子组装

    公开(公告)号：US09210800B1

    公开(公告)日：2015-12-08

    申请号：US14533098

    申请日：2014-11-05

    Applicant: VIA Technologies, Inc.

    Inventor： Sheng-Yuan Lee

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/02 ,  H01P3/08

    CPC classification number: H05K1/0245 ,  H01P3/026 ,  H01P3/08 ,  H05K1/0224 ,  H05K2201/09336 ,  H05K2201/09618

    Abstract: A circuit layout structure is suitable for a circuit board and includes following components. A first differential pair and a second differential pair respectively extend from the inside of a chip area of the circuit board to the outside of the chip area through a first patterned conductive layer of the circuit board, and respectively extend between the chip area and a port area of the circuit board through a second patterned conductive layer of the circuit board. A third differential pair extends from the chip area to the port area through the first patterned conductive layer. A first ground plane is constituted by the first patterned conductive layer. Orthogonal projections of the first differential pair and the second differential pair on the second patterned conductive layer overlap the first ground plane.

    Abstract translation: 电路布局结构适用于电路板，并包括以下部件。 第一差分对和第二差分对分别从电路板的芯片区域的内部经由电路板的第一图案化导电层延伸到芯片区域的外部，并且分别在芯片区域和端口之间延伸 通过电路板的第二图案化导电层的电路板的面积。 第三差分对通过第一图案化导电层从芯片区域延伸到端口区域。 第一接地层由第一图案化导电层构成。 第二图案化导电层上的第一差分对和第二差分对的正交投影与第一接地平面重叠。

    ELECTRONIC COMPONENT HOUSING PACKAGE AND ELECTRONIC APPARATUS
    189.
    发明申请
    ELECTRONIC COMPONENT HOUSING PACKAGE AND ELECTRONIC APPARATUS 有权
    电子元件外壳和电子设备

    公开(公告)号：US20140345929A1

    公开(公告)日：2014-11-27

    申请号：US14367566

    申请日：2012-12-20

    Applicant: KYOCERA Corporation

    Inventor： Mahiro Tsujino ,  Yoshiki Kawazu

    IPC: H05K1/02 ,  H05K1/18

    CPC classification number: H05K1/0213 ,  H01L23/057 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2924/3011 ,  H05K1/024 ,  H05K1/18 ,  H05K2201/09336 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: While it is necessary for an electronic component housing package to be provided with numerous wiring conductors, phase differences of signals caused by differences in signal transmission distance among the wiring conductors, is a problem. An electronic component housing package based on one embodiment includes a substrate having a dielectric region and an electronic component placement region, a frame body surrounding the dielectric region and the placement region, and wiring conductors disposed on the dielectric region of the substrate. The wiring conductors have a first wiring conductor and a second wiring conductor which is longer in signal transmission distance than the first wiring conductor, which are disposed so as to extend from a location immediately below the frame body to the dielectric region. The frame body made of a dielectric material has a projection protruding from its inner periphery, which covers at least part of the first wiring conductor.

    Abstract translation: 虽然电子部件外壳封装需要多个布线导体，但是由布线导体之间的信号传输距离的差异引起的信号的相位差是一个问题。 基于一个实施例的电子部件壳体封装包括具有电介质区域和电子部件放置区域的基板，围绕介电区域和放置区域的框体，以及布置在基板的电介质区域上的布线导体。 所述布线导体具有第一布线导体和第二布线导体，所述第一布线导体和第二布线导体的信号传输距离比所述第一布线导体长，所述第一布线导体和所述第二布线导体被布置为从所述框体正下方的位置延伸到所述电介质 由介电材料制成的框架体具有从其内周突出的突起，其覆盖第一布线导体的至少一部分。

    ELECTRIC MULTILAYER PRINTED CIRCUIT BOARD
    190.
    发明申请
    ELECTRIC MULTILAYER PRINTED CIRCUIT BOARD 审中-公开
    电动多层印刷电路板

    公开(公告)号：US20140345912A1

    公开(公告)日：2014-11-27

    申请号：US14345436

    申请日：2012-08-17

    Applicant: Bernd Eifer ,  Jakob Tschritter

    Inventor： Bernd Eifer ,  Jakob Tschritter

    IPC: H05K1/02

    CPC classification number: H05K1/0216 ,  H05K1/0224 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/0723 ,  H05K2201/09336

    Abstract: The invention relates to an electric multilayer printed circuit board which satisfies the PICMG specification EXP.O, comprising a first signal layer and a second signal layer. The first signal layer comprises at least one first conductive path (33) and a first shielding region. The second signal layer comprises at least one second conductive path (43) and a second shielding region. The at least one first conductive path (33) and the at least one second conductive path (34) can be arranged such that the paths cross in at least one crossing point K. The first conductive path (33) is arranged adjacently to the second shielding region at each point where the first conductive path does not cross a second conductive path (43), and each second conductive path (43) is arranged adjacently to the first shielding region at each point where the second conductive path does not cross a conductive path (33).

    Abstract translation: 本发明涉及一种满足PICMG规范EXP.O的电气多层印刷电路板，包括第一信号层和第二信号层。 第一信号层包括至少一个第一导电路径（33）和第一屏蔽区域。 第二信号层包括至少一个第二导电路径（43）和第二屏蔽区域。 可以布置至少一个第一导电路径（33）和至少一个第二导电路径（34），使得路径在至少一个交叉点K中交叉。第一导电路径（33）被布置成与第二导电路径 在第一导电路径不穿过第二导电路径（43）的每个点处的屏蔽区域，并且每个第二导电路径（43）在第二导电路径不交叉导电的每个点处与第一屏蔽区域相邻布置 路径（33）。

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