公开(公告)号：US20230380062A1

公开(公告)日：2023-11-23

申请号：US17923624

申请日：2021-04-29

Applicant: CORNING INCORPORATED

Inventor： DHANANJAY JOSHI ,  CHUKWUDI AZUBUIKE OKORO ,  SCOTT CHRISTOPHER POLLARD

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/06 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/0306 ,  H05K3/064 ,  H05K3/42 ,  H05K2201/09509 ,  H05K2201/068 ,  H05K2201/09154 ,  H05K2201/0215 ,  H05K2201/09827 ,  H05K2201/09845

Abstract: A substrate including a via with a beveled overburden is disclosed. The substrate can include a substrate having a first surface, a second surface opposite the first surface, and a via passing from the first surface to the second surface. The via can be coated with a metallic layer that includes a first beveled overburden on the first surface, and the first beveled overburden can include a first outer edge that forms a first bevel angle greater than 95° with the first surface. The substrate can include a second beveled overburden that includes a second outer edge that forms a second bevel angle greater than 95° with the second surface. Methods of making the beveled overburdens are also disclosed.

公开(公告)号：US20230319987A1

公开(公告)日：2023-10-05

申请号：US18191062

申请日：2023-03-28

Applicant: IBIDEN CO., LTD.

Inventor： Jun SAKAI ,  Shiho SHIMADA

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/18

CPC classification number: H05K1/0298 ,  H05K1/115 ,  H05K3/424 ,  H05K3/188 ,  H05K2201/09827 ,  H05K2201/096

Abstract: A printed wiring board includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the insulating layer and including a conductor circuit, and a via conductor formed in an opening formed in the insulating layer and connecting the first and second conductor layers. The second conductor layer and via conductor include a seed layer and an electrolytic plating layer formed on the seed layer such that the seed layer has a first layer and a second layer formed on the first layer, the first layer has a width greater than a width of the second layer in cross section of the conductor circuit in the second conductor layer and that the electrolytic plating layer has a width greater than the width of the first layer in cross section of the conductor circuit in the second conductor layer.

公开(公告)号：US11769719B2

公开(公告)日：2023-09-26

申请号：US16017671

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jonathan Rosch ,  Wei-Lun Jen ,  Cheng Xu ,  Liwei Cheng ,  Andrew Brown ,  Yikang Deng

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/111 ,  H05K1/115 ,  H05K1/025 ,  H05K1/18 ,  H05K2201/095 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09827

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US11765833B2

公开(公告)日：2023-09-19

申请号：US17681093

申请日：2022-02-25

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Myeong Hui Jung ,  Seung Eun Lee ,  Yong Hoon Kim

IPC: H05K1/18

CPC classification number: H05K1/186 ,  H05K2201/096 ,  H05K2201/09481 ,  H05K2201/09827

Abstract: A substrate having an electronic component embedded therein includes first and second insulating layers including first and second cavities, respectively, first and second electronic components disposed within the first and second cavities, respectively, a first adhesive layer disposed between the first and second insulating layers, and a connection member penetrating through at least a portion of the first adhesive layer. One end and the other end of the connection member are connected to the first and second electronic components, respectively.

公开(公告)号：US11742255B2

公开(公告)日：2023-08-29

申请号：US17128748

申请日：2020-12-21

Applicant: Gerald Ho Kim

Inventor： Gerald Ho Kim

IPC: H01L23/367 ,  H01L31/0203 ,  H01L31/024 ,  H01L23/051 ,  H01L23/043 ,  H01L31/0232 ,  H01L21/48 ,  H01L23/373 ,  H01S5/024 ,  H05K1/02 ,  H05K1/03 ,  H05K1/14 ,  H01L33/48 ,  H01L33/58 ,  H01L33/64

CPC classification number: H01L23/3672 ,  H01L21/4803 ,  H01L21/4882 ,  H01L23/043 ,  H01L23/051 ,  H01L23/3675 ,  H01L23/3738 ,  H01L31/0203 ,  H01L31/02325 ,  H01S5/02469 ,  H01L31/024 ,  H01L31/02327 ,  H01L33/483 ,  H01L33/58 ,  H01L33/641 ,  H01L33/642 ,  H01L2924/0002 ,  H01L2933/0075 ,  H05K1/0203 ,  H05K1/0274 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/041 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2201/10174 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of a silicon heat-dissipation package for compact electronic devices are described. In one aspect, a device includes first and second silicon cover plates. The first silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The second silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The first primary side of the second silicon cover plate includes an indentation configured to accommodate an electronic device therein. The first primary side of the second silicon cover plate is configured to mate with the second primary side of the first silicon cover plate when the first silicon cover plate and the second silicon cover plate are joined together with the electronic device sandwiched therebetween.

公开(公告)号：US20230262892A1

公开(公告)日：2023-08-17

申请号：US18156736

申请日：2023-01-19

Applicant: AT&S Austria Technologie & Systemtechnik AG

Inventor： Minwoo Lee

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K3/4682 ,  H05K2201/096 ,  H05K2201/09827

Abstract: A coreless component carrier includes a stack with at least two electrically conductive layer structures and at least one electrically insulating layer structure, vias that vertically interconnect the electrically conductive layer structures in the stack, and protruding portions that protrude from the outermost electrically conductive layer structure of the stack beyond the upper main surface of the stack. The vias include an electrically conductive material and taper in the same direction. Methods for manufacturing the coreless component carrier are also disclosed.

公开(公告)号：US11700690B2

公开(公告)日：2023-07-11

申请号：US17457681

申请日：2021-12-06

Applicant: AT&S (China) Co. Ltd.

Inventor： Mikael Tuominen

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/05 ,  H05K3/00 ,  H05K3/02 ,  H05K3/12 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/425 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2203/107

Abstract: A component carrier with a stack including an electrically insulating layer structure and an electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm. A demarcation surface of the plating layer in the blind hole and facing away from the stack extends laterally outwardly from the bottom of the blind hole towards a lateral indentation and extends laterally inwardly from the indentation up to an outer end of the blind hole. An electrically conductive structure fills at least part of a volume between the plating layer and an exterior of the blind hole.

公开(公告)号：US20230209707A1

公开(公告)日：2023-06-29

申请号：US17746372

申请日：2022-05-17

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jung Han KIM ,  Youn Gyu HAN

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/10 ,  H05K3/30

CPC classification number: H05K1/0298 ,  H05K1/115 ,  H05K3/10 ,  H05K3/30 ,  H05K1/0271 ,  H05K2201/2081 ,  H05K2201/09827

Abstract: A printed circuit board includes: a plurality of insulating layers; a plurality of wiring pattern layers disposed on at least one surface of the plurality of insulating layers; a via connecting wiring pattern layers, among the plurality of wiring pattern layers, disposed on upper and lower surfaces of one of the plurality of insulating layers to each other; a connection pad disposed on a surface of an outermost layer among the plurality of insulating layers; and a solder resist having a hole exposing at least a portion of the connection pad. An external surface of the solder resist has surface roughness.

公开(公告)号：US20230156921A1

公开(公告)日：2023-05-18

申请号：US17527687

申请日：2021-11-16

Applicant: Western Digital Technologies, Inc.

Inventor： Uthayarajan A/L Rasalingam ,  Alexander Beh

IPC: H05K1/18 ,  H01L23/00

CPC classification number: H05K1/181 ,  H01L24/16 ,  H01L2224/10135 ,  H01L2224/16225 ,  H05K2201/09827 ,  H05K2201/10159 ,  H01L2924/1438

Abstract: A data storage device includes a substrate and one or more grid array integrated circuit packages. The grid array integrated circuit package includes at least one self-alignment pin having a tapered shape. The substrate includes one or more connection pads to receive the grid array integrated circuit packages. The connection pads include at least one self-alignment receptacle that receives the self-alignment pins such that the grid array integrated circuit packages maintain an alignment with an associated connection pad of the substrate.

公开(公告)号：US20230141270A1

公开(公告)日：2023-05-11

申请号：US17691772

申请日：2022-03-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Chi Seong Kim ,  Won Seok Lee ,  Guh Hwan Lim ,  Jin Uk Lee ,  Jin Oh Park

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/00

CPC classification number: H05K1/119 ,  H05K1/183 ,  H05K3/0038 ,  H05K3/0044 ,  H05K3/0035 ,  H05K2201/09854 ,  H05K2201/09827

Abstract: A printed circuit board includes: a first insulating material; and a second insulating material disposed on one surface of the first insulating material, and including first and second cavities having depths different from each other. At least one groove portion is disposed in a side surface of each of the first and second cavities.