公开(公告)号：US20230402391A1

公开(公告)日：2023-12-14

申请号：US17814527

申请日：2022-07-24

Applicant: Unimicron Technology Corp.

Inventor： Ying-Chu CHEN ,  Jeng-Ting LI ,  Chi-Hai KUO ,  Cheng-Ta KO ,  Pu-Ju LIN

IPC: H01L23/538 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5385 ,  H01L23/5383 ,  H01L23/293 ,  H01L21/4857 ,  H01L21/56

Abstract: A manufacturing method of a package structure includes: forming a redistribution layer on a top surface of a glass substrate; forming a protective layer on the top surface of the glass substrate; cutting the glass substrate and the protective layer such that the glass substrate has a cutting edge, in which a crack is formed in the cutting edge of the glass substrate; and heating the protective layer such that a portion of the protective layer flows towards a bottom surface of the glass substrate to cover the cutting edge of the glass substrate and fill the crack in the cutting edge of the glass substrate.

公开(公告)号：US11792918B2

公开(公告)日：2023-10-17

申请号：US17455918

申请日：2021-11-21

Applicant: Unimicron Technology Corp.

Inventor： Pei-Wei Wang ,  Heng-Ming Nien ,  Ching-Sheng Chen ,  Yi-Pin Lin ,  Shih-Liang Cheng

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/024 ,  H05K1/0222 ,  H05K1/112

Abstract: A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.

公开(公告)号：US20230284376A1

公开(公告)日：2023-09-07

申请号：US17662432

申请日：2022-05-08

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hung KUO

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40

CPC classification number: H05K1/0271 ,  H05K1/181 ,  H05K1/115 ,  H05K3/32 ,  H05K3/40 ,  H05K2201/068 ,  H05K2201/10378

Abstract: An electronic circuit assembly includes an interposer substrate, a wiring substrate, an electrical connective part and an electronic component. The interposer substrate with a first coefficient of thermal expansion (CTE) includes a first surface, a second surface opposite to the first surface, and a first side surface connecting to the first surface and the second surface. The wiring substrate with a second CTE is disposed below the second surface. The first CTE is lower than the second CTE. The electrical connective part is disposed in the interposer substrate and extends to the first side surface. The electronic component is attached to the first side surface and is electrically connected to the electrical connective part.

公开(公告)号：US11737209B2

公开(公告)日：2023-08-22

申请号：US17574551

申请日：2022-01-13

Applicant: Unimicron Technology Corp.

Inventor： Chih-Chiang Lu ,  Chi-Min Chang ,  Shao-Chien Lee ,  Jun-Rui Huang ,  Ming-Ting Chang

IPC: H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10

CPC classification number: H05K1/024 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/10 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/0183 ,  H05K2201/09209 ,  H05K2203/0502

Abstract: A circuit board includes a first dielectric material, a second dielectric material, a third dielectric material, a first external circuit layer, a second external circuit layer, multiple conductive structures, and a conductive via structure. Dielectric constants of the first, the second and the third dielectric materials are different. The first and the second external circuit layers are respectively disposed on the first and the third dielectric materials. The conductive via structure at least penetrates the first and the second dielectric materials and is electrically connected to the first and the second external circuit layers to define a signal path. The conductive structures are electrically connected to each other and surround the first, the second and the third dielectric materials. The conductive structures are electrically connected to the first and the second external circuit layers to define a ground path surrounding the signal path.

公开(公告)号：US11715715B2

公开(公告)日：2023-08-01

申请号：US17200922

申请日：2021-03-15

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Ming-Ru Chen ,  Cheng-Chung Lo ,  Chin-Sheng Wang ,  Wen-Sen Tang

IPC: H01L23/00 ,  H01L25/075 ,  H01L27/12 ,  H01L33/62

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L25/0753 ,  H01L27/1214 ,  H01L33/62 ,  H01L2224/03312 ,  H01L2224/03552 ,  H01L2224/0401 ,  H01L2224/0518 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05193 ,  H01L2224/11464 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/12041 ,  H01L2924/1426 ,  H01L2933/0066

Abstract: A manufacturing method of a metal bump structure is provided. A driving base is provided. At least one pad and an insulating layer are formed on the driving base. The pad is formed on an arrangement surface of the driving base and has an upper surface. The insulating layer covers the arrangement surface of the driving base and the pad, and exposes a part of the upper surface of the pad. A patterned metal layer is formed on the upper surface of the pad exposed by the insulating layer, and extends to cover a part of the insulating layer. An electro-less plating process is performed to form at least one metal bump on the patterned metal layer. A first extension direction of the metal bump is perpendicular to a second extension direction of the driving base.

公开(公告)号：US11710690B2

公开(公告)日：2023-07-25

申请号：US17233551

申请日：2021-04-19

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Chi-Hai Kuo ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238

Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.

公开(公告)号：US20230231087A1

公开(公告)日：2023-07-20

申请号：US17653659

申请日：2022-03-07

Applicant: Unimicron Technology Corp.

Inventor： Hao-Wei TSENG ,  Chi-Hai KUO ,  Jeng-Ting LI ,  Ying-Chu CHEN ,  Pu-Ju LIN ,  Cheng-Ta KO

IPC: H01L33/54 ,  H01L25/075 ,  H01L23/00

CPC classification number: H01L33/54 ,  H01L25/0753 ,  H01L24/83 ,  H01L2933/005 ,  H01L24/29 ,  H01L2224/29194 ,  H01L2224/83099 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/8389 ,  H01L2224/83856 ,  H01L24/32 ,  H01L2224/32227 ,  H01L2924/12041

Abstract: A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.

公开(公告)号：US11690180B2

公开(公告)日：2023-06-27

申请号：US17147474

申请日：2021-01-13

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tse-Wei Wang

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/03 ,  H05K3/40

CPC classification number: H05K3/4644 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/4007 ,  H05K3/4038 ,  H05K2201/0175

Abstract: A manufacturing method of a carrier structure includes: A build-up circuit layer is formed on a carrier. The build-up circuit layer includes at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on the carrier and includes at least one first pad, which is disposed relative to at least one through hole of the carrier. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive via penetrates the first dielectric layer and is electrically connected to the first circuit layer and the second circuit layer.

公开(公告)号：US11682612B2

公开(公告)日：2023-06-20

申请号：US17235944

申请日：2021-04-21

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chi-Hai Kuo ,  Chia-Yu Peng ,  Tzyy-Jang Tseng

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/1434 ,  H01L2924/14335 ,  H01L2924/35

Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

公开(公告)号：US11641713B2

公开(公告)日：2023-05-02

申请号：US17483824

申请日：2021-09-24

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hung Kuo ,  Kuo-Ching Chen

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K3/00

Abstract: A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.