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公开(公告)号：US08877629B2
公开(公告)日：2014-11-04
申请号：US13743450
申请日：2013-01-17
Applicant: Chipbond Technology Corporation
Inventor： Cheng-Hung Shih , Yung-Wei Hsieh , Kai-Yi Wang
IPC: H01L21/44 , H01L23/498 , H01L21/768 , H01L23/00
CPC classification number: H01L23/562 , H01L23/3171 , H01L23/3192 , H01L23/48 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0361 , H01L2224/0401 , H01L2224/05022 , H01L2224/05166 , H01L2224/05558 , H01L2224/05572 , H01L2224/0558 , H01L2224/05647 , H01L2224/05655 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/131 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/014
Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.
Abstract translation: 半导体制造方法包括以下步骤：提供具有至少一个连接焊盘和保护层的硅衬底，形成具有至少一个第一部分和至少一个第二部分的第一种子层，形成第一光致抗蚀剂层，形成第 第一缓冲层，具有耦合部分和包层部分，去除第一光致抗蚀剂层，去除第一种子层的第二部分以形成第一凸块下金属层，在保护层和第一缓冲层上形成支撑层， 所述第一凸块下金属层具有第一环壁，所述第一缓冲层具有第二环壁，所述第一环壁，所述第二环壁和所述包层部由所述支撑层包覆，并且形成连接部和覆盖层 与连接部分的联接部分。
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公开(公告)号：US12224734B2
公开(公告)日：2025-02-11
申请号：US17856036
申请日：2022-07-01
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Cheng-Hung Shih , Cheng-Fan Lin
Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.
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公开(公告)号：US20220337216A1
公开(公告)日：2022-10-20
申请号：US17856036
申请日：2022-07-01
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Cheng-Hung Shih , Cheng-Fan Lin
IPC: H03H9/02 , H01L41/047 , H03H9/05 , H03H9/145
Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.
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14.发明申请公开(公告)号：US20160318756A1
公开(公告)日：2016-11-03
申请号：US14736328
申请日：2015-06-11
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Cheng-Hung Shih , Yung-Wei Hsieh , Shu-Chen Lin , Fu-Yen Ho , Yen-Ting Chen
IPC: B81C1/00
CPC classification number: H01L23/10 , B81C1/00269 , B81C2203/019 , H01L21/50
Abstract: A process for manufacturing a semiconductor package having a hollow chamber includes providing a bottom substrate having a bottom plate, a ring wall and a slot, wherein the ring wall and the bottom plate form the slot; forming an under ball metallurgy layer on a surface of the ring wall;bumping a plurality of solder balls on a surface of the under ball metallurgy layer, each of the solder balls comprises a diameter, wherein a spacing is spaced apart between two adjacent solder balls; performing reflow soldering to the solder balls for making the solder balls melting and interconnecting to form a connection layer; connecting a top substrate to the bottom substrate, wherein the lot of the bottom substrate is sealed by the top substrate to form a hollow chamber used for accommodating an electronic device.
Abstract translation: 在球形冶金层的表面上碰撞多个焊球，每个焊球包括直径，其中间隔在两个相邻的焊球之间间隔开; 对所述焊球进行回流焊接，以使所述焊球熔化并互连以形成连接层; 将顶部基板连接到底部基板，其中底部基板的批次被顶部基板密封以形成用于容纳电子设备的中空室。
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公开(公告)号：US20140159234A1
公开(公告)日：2014-06-12
申请号：US13743450
申请日：2013-01-17
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Cheng-Hung Shih , Yung-Wei Hsieh , Kai-Yi Wang
IPC: H01L23/498 , H01L21/768
CPC classification number: H01L23/562 , H01L23/3171 , H01L23/3192 , H01L23/48 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0361 , H01L2224/0401 , H01L2224/05022 , H01L2224/05166 , H01L2224/05558 , H01L2224/05572 , H01L2224/0558 , H01L2224/05647 , H01L2224/05655 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/131 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/014
Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.
Abstract translation: 半导体制造方法包括以下步骤：提供具有至少一个连接焊盘和保护层的硅衬底，形成具有至少一个第一部分和至少一个第二部分的第一种子层，形成第一光致抗蚀剂层，形成第 第一缓冲层，具有耦合部分和包层部分，去除第一光致抗蚀剂层，去除第一种子层的第二部分以形成第一凸块下金属层，在保护层和第一缓冲层上形成支撑层， 所述第一凸块下金属层具有第一环壁，所述第一缓冲层具有第二环壁，所述第一环壁，所述第二环壁和所述包层部由所述支撑层包覆，并且形成连接部和覆盖层 与连接部分的联接部分。
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Patent Agency Ranking
公开(公告)号：US20130256882A1
公开(公告)日：2013-10-03
申请号：US13903447
申请日：2013-05-28
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Cheng-Hung Shih , Yung-Wei Hsieh , Shu-Chen Lin , Cheng-Fan Lin , Hua-An Dai
IPC: H01L23/58 , H01L23/498
CPC classification number: H01L23/58 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/034 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05099 , H01L2224/05572 , H01L2224/05666 , H01L2224/1147 , H01L2224/11472 , H01L2224/11906 , H01L2224/13082 , H01L2224/13147 , H01L2224/13562 , H01L2224/13564 , H01L2224/13582 , H01L2224/13583 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2924/00013 , H01L2924/00014 , H01L2224/13099 , H01L2224/05599 , H01L2224/05552
Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.
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公开(公告)号：US20130252374A1
公开(公告)日：2013-09-26
申请号：US13893620
申请日：2013-05-14
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Cheng-Hung Shih , Shu-Chen Lin , Cheng-Fan Lin , Yung-Wei Hsieh , Bo-Shiun Jiang
IPC: H01L21/50
CPC classification number: H01L21/50 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/2929 , H01L2224/293 , H01L2224/29393 , H01L2224/29499 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81903 , H01L2224/83192 , H01L2224/83851 , H01L2224/9211 , H01L2924/00012 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2924/00
Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances.
Abstract translation: 半导体封装方法包括提供具有多个焊盘的衬底，每个焊盘包括具有多个第一导电接触区域和多个第一非导电接触区域的第一耦合表面; 在基板上形成具有抗解离功能的导电凝胶，所述可导电凝胶包括多个导电颗粒和多个抗分解物质; 将芯片安装在基板上，所述芯片包括多个含铜凸块，每个含铜凸块包括环表面和具有多个第二导电接触区域和多个第二非导电性接触区域的第二耦合表面 接触区域，其中所述导电颗粒与所述第一导电接触区域和所述第二导电接触区域电连接，所述抗分解物质与所述第二非导电接触区域接触，并且所述环形表面被所述反 - 解离物质
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公开(公告)号：US20130249089A1
公开(公告)日：2013-09-26
申请号：US13893623
申请日：2013-05-14
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Cheng-Hung Shih , Yung-Wei Hsieh , Shu-Chen Lin , Cheng-Fan Lin , Hua-An Dai
IPC: H01L23/498
CPC classification number: H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/034 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05571 , H01L2224/05666 , H01L2224/11472 , H01L2224/11906 , H01L2224/13007 , H01L2224/13147 , H01L2224/13562 , H01L2224/13582 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2924/00014 , H01L2924/01074 , H01L2924/01079 , H01L2924/01029 , H01L2224/05552
Abstract: A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion.
Abstract translation: 制造细间距凸块的方法包括以下步骤：提供硅衬底; 在所述硅衬底上形成含钛金属层，其中所述含钛金属层包括多个第一区和多个第二区; 在含钛金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层以形成多个开口槽; 在开口槽处形成多个铜凸块，其中每个铜凸块包括第一顶表面和环表面; 加热光致抗蚀剂层以形成多个主体部分和多个可移除部分; 蚀刻光致抗蚀剂层; 以及移除所述第二区域以使得所述第一区域中的每一个能够形成具有轴承部分和延伸部分的凸起下金属层。
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公开(公告)号：US20210013865A1
公开(公告)日：2021-01-14
申请号：US16581901
申请日：2019-09-25
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Cheng-Hung Shih , Cheng-Fan Lin
IPC: H03H9/02 , H03H9/05 , H01L41/047 , H03H9/145
Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.
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公开(公告)号：US20200295123A1
公开(公告)日：2020-09-17
申请号：US16885461
申请日：2020-05-28
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Cheng-Hung Shih , Nian-Cih Yang , Yi-Cheng Chen , Shang-Jan Yang
Abstract: A semiconductor device having 3D inductor includes a first transverse inductor, a longitudinal inductor and a second transverse inductor. The first transverse inductor is formed on a first substrate, the second transverse inductor and the longitudinal inductor are formed on a second substrate. The second substrate is bonded to the first substrate to connect the first transverse inductor and the longitudinal inductor such that the first transverse inductor, the longitudinal inductor and the second transverse inductor compose a 3D inductor.
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