公开(公告)号：US20250031317A1

公开(公告)日：2025-01-23

申请号：US18765342

申请日：2024-07-08

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  Heesoo LEE

IPC: H05K3/34 ,  H05K1/18

Abstract: A method for mounting an electronic device on a flexible substrate is disclosed. The method comprising: providing the flexible substrate with conductive patterns on its front surface; forming solder bumps on the conductive patterns; dispensing a thermosetting material on the front surface of the flexible substrate; attaching the electronic device on the flexible substrate via the solder bumps and the thermosetting material; heating the flexible substrate to a first temperature to cure the thermosetting material; and heating the flexible substrate to a second temperature higher than the first temperature to reflow the solder bumps.

公开(公告)号：US20240332050A1

公开(公告)日：2024-10-03

申请号：US18613170

申请日：2024-03-22

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  DaYoung KWON ,  YuJin HWANG

IPC: H01L21/673

CPC classification number: H01L21/67373

Abstract: A carrier assembly comprises a carrier main body comprising a housing, the housing comprising side walls having supporting slots for carrying the semiconductor package strips inside the housing, respectively, and the housing defining a front opening and a rear opening between the side walls to allow for placement and displacement of the semiconductor package strips, and a pair of clamping devices for applying clamping forces to the semiconductor package strips against the supporting slots, respectively, and each of the pair of clamping device comprising a locking plate, strip contacting extensions extending from the locking plate and insertable through one of the front opening and the rear opening of the housing, and a locking member for moving the strip contacting extensions between a locked position and an unlocked position, wherein in the locked position the substrate package strips are pressed against the supporting slots by the respective strip contacting extensions.

公开(公告)号：US20240120289A1

公开(公告)日：2024-04-11

申请号：US18475249

申请日：2023-09-27

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  YeJin PARK ,  HeeSoo LEE

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/16155 ,  H01L2224/16225 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2924/142 ,  H01L2924/1431 ,  H01L2924/182 ,  H01L2924/3025

Abstract: An electronic package is provided. The electronic package comprises a substrate having a first region and a second region; a first set of electronic components mounted on the substrate in the first region; a second set of electronic components mounted on the substrate in the second region; an encapsulant layer disposed on the substrate and encapsulating the first and second sets of electronic components; a set of interconnect components disposed on the substrate in the second region, and extending through the encapsulant layer, wherein the set of interconnect components are electrically coupled to the first and second sets of electronic components; and a connector mounted on the encapsulant layer and electrically coupled to the first and second sets of electronic components through the set of interconnect components.

公开(公告)号：US20240098907A1

公开(公告)日：2024-03-21

申请号：US18459008

申请日：2023-08-30

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： HyoDong RYU ,  SeungHyun LEE ,  WonSang RHEE ,  HunTaek LEE ,  KyoungHee PARK

IPC: H05K3/34

CPC classification number: H05K3/3485 ,  H05K3/3436

Abstract: Provided is a method for forming an electronic package, comprising: providing a substrate comprising a first set of conductive pads at which a set of terminals of a first electronic component are to be mounted, respectively; forming solder paste on each of the first set of conductive pads, wherein the solder paste exposes a portion of a surface of a conductive pad that is facing away from the others of the first set of conductive pads but does not substantially expose another portion of the surface of the conductive pad that is facing towards the others of the first set of conductive pads; placing the first electronic component on the substrate with the set of terminals of the first electronic component aligned with the first set of conductive pads; reflowing the solder paste on the first set of conductive pads to secure the first electronic component onto the substrate.

公开(公告)号：US20250140773A1

公开(公告)日：2025-05-01

申请号：US18926424

申请日：2024-10-25

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HeeSoo LEE

IPC: H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L25/10

Abstract: A method for forming the same is provided. The method comprises: providing a package substrate; attaching back conductive blocks onto a back surface of the package substrate via back solder bump; loading the package substrate on a first bottom chase with the back conductive blocks facing upward, and pressing, with a first top chase, the back conductive blocks against the first bottom chase to reshape the back solder bumps and horizontally align top surfaces of the back conductive blocks with each other; attaching front conductive blocks onto a front surface of the package substrate via front solder bumps; loading the package substrate on a second bottom chase with the front conductive blocks facing upward, and pressing, with a second top chase, the front conductive blocks against the second bottom chase to reshape the front solder bumps and horizontally align top surfaces of the front conductive blocks with each other.

公开(公告)号：US20250125295A1

公开(公告)日：2025-04-17

申请号：US18829324

申请日：2024-09-10

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  SangJun PARK ,  NamGu KIM ,  GyeongMin KIM ,  JiYeon KIM ,  SoYeong LEE

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

Abstract: A semiconductor package and a method for making the same are provided. The method includes: providing a package substrate having a first surface and a second surface opposite to the first surface; mounting a plurality of conductive blocks onto the first surface of the package substrate; forming at least one conductive bump on each of the conductive blocks; forming a first encapsulant on the first surface of the package substrate to encapsulate the conductive blocks and the conductive bump on each of the conductive blocks; and grinding the first encapsulant to remove an upper portion of the first encapsulant and an upper portion of the conductive bump on each of the conductive blocks, such that an exposed surface of the conductive bump on each of the conductive blocks is at a same height relative to the first surface of the package substrate.

公开(公告)号：US20250105194A1

公开(公告)日：2025-03-27

申请号：US18896961

申请日：2024-09-26

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  SangHoon LEE ,  DoYeon PARK ,  SangJun PARK ,  JaeKyung JEON

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L25/18

Abstract: A method for forming conductive blocks on a package substrate, a semiconductor package and a method for forming the same is provided. The method for forming conductive blocks on a package substrate comprises: providing a package substrate with multiple sets of conductive pads formed thereon; depositing a solder material onto the package substrate to form solder bumps on the multiple sets of conductive pads; attaching multiple conductive blocks onto the package substrate, wherein each of the multiple conductive bloc aligned with one of the multiple sets of conductive pads; loading the package substrate on a bottom chase with the multiple conductive blocks facing upward; and pressing, with a top chase, the conductive blocks against the bottom chase to reshape the solder bumps and horizontally align top surfaces of the multiple conductive blocks with each other.

公开(公告)号：US20240347509A1

公开(公告)日：2024-10-17

申请号：US18636301

申请日：2024-04-16

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： HyeonChul LEE ,  KyoungHee PARK ,  KyungHwan KIM ,  SeungHyun LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/60 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/3121 ,  H01L23/60 ,  H01L24/94 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/1815

Abstract: A semiconductor package strip is provided. The semiconductor package strip includes: a substrate; a first set of electronic components and a first external connector attached on the substrate; a second set of electronic components and a second external connector attached on the substrate; wherein the first set of electronic components are adjacent to the second set of electronic components, and the first and second external connectors are disposed at two sides of the first and second sets of electronic components, respectively; an encapsulant layer formed on the substrate, wherein the encapsulant covers the first and second sets of electronic components but exposes the first and second external connectors; and a saw street in between the first and second sets of electronic components that allows for singulation of the semiconductor package strip at the saw street.

公开(公告)号：US20240071991A1

公开(公告)日：2024-02-29

申请号：US18451115

申请日：2023-08-17

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  KyoungHee PARK ,  HunTaek LEE ,  KyungHwan KIM ,  WonSang RHEE

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01L24/97 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/97 ,  H01L2924/1421 ,  H01L2924/15153 ,  H01L2924/1811

Abstract: A method for making an electronic package is provided. The method includes providing a substrate strip comprising substrate assemblies, each substrate assembly comprises a first substrate and a second substrate connected to the first substrate via a flexible link, the first substrate comprises a first mounting surface, the second substrate comprises a second mounting surface that is not at a same side of the substrate assembly as the first mounting surface; disposing the substrate strip on a first carrier; attaching a first electronic component onto the first mounting surface; disposing the substrate strip on a second carrier with a plurality of cavities, the first electronic component is received within one of the plurality of cavities; attaching a second electronic component onto the second mounting surface; singulating the substrate assemblies from each other; and bending the flexible link to form an angle between the first substrate and the second substrate.