公开(公告)号：US09565464B2

公开(公告)日：2017-02-07

申请号：US14988338

申请日：2016-01-05

Applicant: MaxLinear, Inc.

Inventor： Anand Anandakumar ,  Sheng Ye ,  Curtis Ling

IPC: G06F3/00 ,  H03K9/00 ,  H04N21/426 ,  H04N5/44 ,  H04N5/50 ,  H04N21/438 ,  H04N21/443 ,  H04N21/462 ,  H04N21/61

CPC classification number: H04N21/4263 ,  H04N5/44 ,  H04N5/50 ,  H04N21/4383 ,  H04N21/4436 ,  H04N21/4622 ,  H04N21/6143

Abstract: Methods and systems for multi-path video and network channels may comprise a communication device comprising a wideband path (WB) and a narrowband path (NB). A video channel and a network channel may be received in the WB when the device is operating in a first stage. A video channel and a network channel may be received in the WB and the network channel may also be received in the NB when the device is operating in a second stage. The network channel may be received in the NB when the device is operating in a third stage. The reception of the network channel from both the WB and NB may enable a continuous reception of the network channel in a transition between the first and third stages. The WB may be operable to receive a plurality of channels and the NB may be operable to receive a single channel.

Abstract translation: 用于多路径视频和网络信道的方法和系统可以包括包括宽带路径（WB）和窄带路径（NB）的通信设备。 当设备在第一阶段中操作时，可以在WB中接收视频信道和网络信道。 在WB中可以接收视频信道和网络信道，并且当设备在第二阶段中操作时，也可以在NB中接收网络信道。 当设备在第三阶段中操作时，可以在NB中接收网络信道。 来自WB和NB的网络信道的接收可以在第一和第三阶段之间的转变中实现网络信道的连续接收。 WB可以用于接收多个信道，并且NB可以用于接收单个信道。

公开(公告)号：US20160373212A1

公开(公告)日：2016-12-22

申请号：US15185429

申请日：2016-06-17

Applicant: Maxlinear, Inc.

Inventor： Curtis Ling ,  Sheng Ye

IPC: H04L1/00 ,  H04L7/00

CPC classification number: H04L7/0075 ,  H04B10/40 ,  H04B10/5057 ,  H04L1/0047 ,  H04L7/0079 ,  H04L25/03

Abstract: A method and system for duty-cycled high speed clock and data recovery with forward error correction are provided. The system operates on a first digital signal comprising a first plurality of samples and a second digital signal comprising a second plurality of samples. The second plurality of samples may be a subset of the first plurality of samples, for example, if the first and second pluralities of samples are generated by one analog-to-digital converter. A clock and data recovery module is operable to produce a timing indication according the second digital signal. The second plurality of samples is sampled intermittently. The discontinuity between bursts of samples in the second signal corresponds to a duty cycle. A forward error correction module is operable to produce a digital error-corrected signal according to the first digital signal and the timing indication.

Abstract translation: 提供了一种采用前向纠错的占空比高速时钟和数据恢复方法和系统。 该系统对包括第一多个样本的第一数字信号和包括第二多个样本的第二数字信号进行操作。 第二多个样本可以是第一多个样本的子集，例如，如果第一和第二多个采样由一个模数转换器产生。 时钟和数据恢复模块可操作以根据第二数字信号产生定时指示。 间歇地采样第二多个采样。 第二信号中样本脉冲之间的不连续性对应于占空比。 前向纠错模块可操作以根据第一数字信号和定时指示产生数字纠错信号。

公开(公告)号：US20160322985A1

公开(公告)日：2016-11-03

申请号：US15151042

申请日：2016-05-10

Applicant: MaxLinear, Inc.

Inventor： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06

CPC classification number: H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

Abstract: Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions

Abstract translation: 提供了用于在信号处理期间检测元稳定性的系统和方法。 元稳定性检测器可以包括定时控制电路，多个信号调整电路和多个信号状态电路。 定时控制电路可以测量模数转换期间每个转换周期的比较时间。 每个信号调整电路可以向信号调整电路的一个或多个输入信号施加逻辑运算，并提供对应的输出信号。 至少一个处理周期，每个信号状态电路可以将与一个或多个输入信号有关的状态信息存储到信号状态电路; 并基于先前存储的信息提供输出信号。 多个信号状态电路，多个信号调节电路和定时控制电路可以被布置为在模数转换期间产生用于控制模数转换器（ADC）的一个或多个控制信号

公开(公告)号：US20160182160A1

公开(公告)日：2016-06-23

申请号：US15056229

申请日：2016-02-29

Applicant: MaxLinear, Inc.

Inventor： Kishore Seendripu ,  Raymond Montemayor ,  Sheng Ye ,  Glenn Chang ,  Curtis Ling

IPC: H04B15/00 ,  H04J1/18 ,  H04L27/34

CPC classification number: H04B1/26 ,  H03D3/007 ,  H03D3/008 ,  H03D3/009 ,  H03D7/14 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0086 ,  H03H11/22 ,  H04B1/10 ,  H04B1/109 ,  H04B1/12 ,  H04B1/30 ,  H04B15/00 ,  H04J1/18 ,  H04L27/34

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

公开(公告)号：US20160127027A1

公开(公告)日：2016-05-05

申请号：US14931103

申请日：2015-11-03

Applicant: Maxlinear, Inc.

Inventor： Curtis Ling ,  Sheng Ye

IPC: H04B7/08 ,  H04B10/40 ,  H04B1/40 ,  H01Q3/24 ,  H04B1/7097

CPC classification number: H04B7/086 ,  H01Q3/24 ,  H01Q3/247 ,  H01Q3/267 ,  H04B7/0617 ,  H04B10/25752 ,  H04B10/40 ,  H04B10/43 ,  H04B17/0085 ,  H04B17/12 ,  H04B2201/709709

Abstract: Each of a plurality of modules comprises a respective one of a plurality of antenna elements, and each of a subset of the plurality of modules comprising a respective one of a plurality of transceivers, wherein the plurality of modules are interconnected via one or more communication links. The circuitry may be operable to receive a calibration signal via the plurality of antenna elements, determine, for each one of the antenna elements, a time and/or phase of arrival of the calibration signal, calculate, based on the time and/or phase of arrival of the calibration signal at each of the plurality of antenna elements, electrical distances between the plurality of antenna elements on the one or more communication links, and calculate beamforming coefficients for use with the plurality of antenna elements based on the electrical distances.

Abstract translation: 多个模块中的每一个包括多个天线元件中的相应一个，并且多个模块的子集中的每一个包括多个收发器中的相应一个，其中多个模块经由一个或多个通信链路 。 该电路可操作以经由多个天线元件接收校准信号，为每个天线元件确定校准信号的到达时间和/或相位，基于时间和/或相位来计算 所述校准信号到达所述多个天线元件中的每一个时，所述一个或多个通信链路上的所述多个天线元件之间的电距离，以及基于所述电气距离计算与所述多个天线元件一起使用的波束成形系数。

公开(公告)号：US20160099737A1

公开(公告)日：2016-04-07

申请号：US14966660

申请日：2015-12-11

Applicant: MaxLinear, Inc.

Inventor： Kishore Seendripu ,  Raymond Montemayor ,  Sheng Ye ,  Glenn Chang ,  Curtis Ling

IPC: H04B1/30 ,  H03D7/14 ,  H03D7/16

CPC classification number: H04B1/26 ,  H03D3/007 ,  H03D3/008 ,  H03D3/009 ,  H03D7/14 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0086 ,  H03H11/22 ,  H04B1/10 ,  H04B1/109 ,  H04B1/12 ,  H04B1/30 ,  H04B15/00 ,  H04J1/18 ,  H04L27/34

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

公开(公告)号：US20160006450A1

公开(公告)日：2016-01-07

申请号：US14812327

申请日：2015-07-29

Applicant: MaxLinear, Inc.

Inventor： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06

CPC classification number: H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

Abstract: Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels.

Abstract translation: 提供了用于控制信号处理输出的方法和系统。 在信号处理电路中，通过多个量化级别搜索与模拟输入匹配的量化级别，以及当在特定时间量内搜索失败时，调整信号处理电路的输出的至少一部分。 调整包括将输出的至少部分设置为预定值。 设置输出或其部分可以包括在正常处理路径的输出和被配置用于处理搜索失败的代码生成路径的输出之间进行选择。 可以产生用于控制信号处理电路的输出的产生的定时信息。 定时信息可以用于在通过多个量化级别的搜索期间测量每周期操作时间。

公开(公告)号：US09124291B2

公开(公告)日：2015-09-01

申请号：US13945579

申请日：2013-07-18

Applicant: MaxLinear, Inc.

Inventor： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/12 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.

Abstract translation: 用于处理信号的系统可以被配置为在数字转换到模拟信号期间检测包括元稳定性事件的特定错误的发生，并且处理任何检测到的元稳定性事件，例如通过调整相应数字的至少一部分 基于元稳定事件检测的输出。 数字输出的调整可以包括至少设置数字输出的一部分，诸如多个预定数字值或模式之一。 系统可以包括用于生成和/或输出预定数字值或码型的码发生器。 系统可以包括选择器，用于针对数字输出的部分，在正常处理路径的输出之间和预定义的值或模式之间自适应地选择。

公开(公告)号：US10326462B2

公开(公告)日：2019-06-18

申请号：US16154167

申请日：2018-10-08

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Gallagher

IPC: H03M1/06 ,  H03M1/50 ,  H03M1/10 ,  H03M1/12 ,  H04L7/00 ,  H04L25/08 ,  H04W56/00

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

公开(公告)号：US20190068227A1

公开(公告)日：2019-02-28

申请号：US16171463

申请日：2018-10-26

Applicant: Maxlinear, Inc.

Inventor： Subramanian Anantharaman Chandrasekarapuram ,  Anand Anandakumar ,  Stephane Laurent-Michel ,  Sheng Ye ,  Raja Pullela ,  Glenn Chang ,  Vamsi Paidi

IPC: H04B1/10

Abstract: A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.