公开(公告)号：US20080119051A1

公开(公告)日：2008-05-22

申请号：US11562443

申请日：2006-11-22

Applicant: Suryadevara V. Babu ,  Anita Natarajan ,  Sharath Hegde

Inventor： Suryadevara V. Babu ,  Anita Natarajan ,  Sharath Hegde

IPC: H01L21/304

CPC classification number: H01L21/3212 ,  B81C1/00595 ,  B81C1/00611 ,  B81C2201/0104 ,  B81C2201/0126 ,  C09G1/02 ,  C09K3/1463

Abstract: A method of removing polysilicon in preference to silicon dioxide and/or silicon nitride by chemical mechanical polishing. The method removes polysilicon from a surface at a high removal rate while maintaining a high selectivity of polysilicon to silicon dioxide and/or a polysilicon to silicon nitride. The method is particularly suitable for use in the fabrication of MEMS devices.

Abstract translation: 通过化学机械抛光优选去除二氧化硅和/或氮化硅的多晶硅的方法。 该方法以高去除率从表面去除多晶硅，同时保持多晶硅对二氧化硅和/或多晶硅与氮化硅的高选择性。 该方法特别适用于MEMS器件的制造。

公开(公告)号：US20050052092A1

公开(公告)日：2005-03-10

申请号：US10492896

申请日：2002-09-05

Applicant: Franz Laermer

Inventor： Franz Laermer

IPC: B81B3/00 ,  B81C1/00 ,  G01C19/5712 ,  G01P15/00 ,  H01L41/08

CPC classification number: G01C19/5712 ,  B81B3/0086 ,  B81B2201/0242 ,  B81B2203/0136 ,  B81B2203/033 ,  B81C1/00801 ,  B81C2201/0104 ,  B81C2201/016

Abstract: A micromechanical component and a method for producing the component are provided. The micromechanical component includes a substrate and a micromechanical functional layer of a first material provided over the substrate. The functional layer has a first and second regions, which are connected by a third region of a second material, and at least one of the regions is part of a movable structure, which is suspended over the substrate.

Abstract translation: 提供微机械部件及其制造方法。 微机械部件包括衬底和设置在衬底上的第一材料的微机械功能层。 功能层具有通过第二材料的第三区域连接的第一和第二区域，并且至少一个区域是悬浮在基板上的可移动结构的一部分。

公开(公告)号：US20030197176A1

公开(公告)日：2003-10-23

申请号：US10128368

申请日：2002-04-22

Applicant: Glimmerglass Networks, Inc.

Inventor： James P. Spallas ,  Andres Fernandez ,  Thomas DeBey ,  Lawrence P. Muray

IPC: H01L029/04

CPC classification number: B81C1/00119 ,  B81B2201/042 ,  B81C2201/0104 ,  B81C2201/014 ,  B81C2201/017 ,  B81C2201/019

Abstract: Method for fabricating ultrathin gaps producing ultrashort standoffs in array structures includes sandwiching a patterned device layer between a silicon standoff layer and a silicon support layer, providing that the back surfaces of the respective silicon support layer and the standoff layer are polished to a desired thickness corresponding to the desired standoff height on one side and to at least a minimum height for mechanical strength on the opposing side, as well as to a desired smoothness. Standoffs and mechanical supports are then fabricated by etching to produce voids with the dielectric oxides on both sides of the device layer serving as suitable etch stops. Thereafter, the exposed portions of the oxide layers are removed to release the pattern, and a package layer is mated with the standoff voids to produce a finished device. The standoff layer can be fabricated to counteract curvature.

Abstract translation: 用于制造在阵列结构中产生超短距离的超薄间隙的方法包括在硅隔离层和硅支撑层之间夹着图案化的器件层，条件是相应的硅支撑层和支座层的背面被抛光到相应的所需厚度 达到一侧上所需的间隔高度，并且至少在相对侧上的机械强度的最小高度以及期望的平滑度。 然后通过蚀刻制造支座和机械支撑件以产生空隙，其中装置层两侧的电介质氧化物用作合适的蚀刻停止点。 此后，去除氧化物层的暴露部分以释放图案，并且将封装层与间隙空隙配合以产生成品装置。 可以制造隔离层以抵消曲率。

公开(公告)号：US20030139014A1

公开(公告)日：2003-07-24

申请号：US10269256

申请日：2002-10-11

Inventor： Khalil Najafi ,  Chou Tsung-Kuan

IPC: H01L021/331

CPC classification number: B81C1/00103 ,  B81B2203/0392 ,  B81C1/00547 ,  B81C1/00626 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2201/0133 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3083 ,  Y10S438/974 ,  Y10S438/977

Abstract: A method of fabricating a device having a desired non-planar surface or profile and device produced thereby are provided. A silicon wafer is first coated with silicon nitride, patterned, and DRIE to obtain the desired etch profile. Silicon pillars between trenches are then etched using an isotropic wet etch, resulting in a curved well. The wafer is then oxidized to null2 nullm to smooth the surface of the well, and to protect the well from an ensuing planarization process. The nitride is then selectively removed, and the wafer surface is planarized by removing the Si left in the field regions using either a maskless DRIE or CMP. Finally, the oxide is etched away to produce a wafer with a curved surface.

Abstract translation: 提供一种制造具有期望的非平面表面或轮廓的装置的方法以及由此制造的装置。 硅晶片首先用氮化硅，图案化和DRIE涂覆以获得所需的蚀刻轮廓。 然后使用各向同性的湿蚀刻蚀刻沟槽之间的硅柱，得到弯曲的井。 然后将晶片氧化至〜2μm以平滑孔的表面，并保护井不受随后的平坦化过程的影响。 然后选择性地去除氮化物，并且通过使用无掩模DRIE或CMP去除场区域中留下的Si来平坦化晶片表面。 最后，将氧化物蚀刻掉以产生具有弯曲表面的晶片。

公开(公告)号：US20020168810A1

公开(公告)日：2002-11-14

申请号：US10112593

申请日：2002-03-29

Applicant: The Penn State Research Foundation

Inventor： Thomas N. Jackson

IPC: H01L021/00

CPC classification number: B81C1/00126 ,  B81C2201/0104 ,  B81C2201/019 ,  B82B3/00 ,  B82Y30/00 ,  B82Y40/00

Abstract: The present invention is directed to a process for forming one or more lateral nanostructures on a substrate. The process comprises the steps of: providing a substrate; depositing a first layer on the substrate; forming at least one edge on the first layer; depositing at least one separation layer on the first layer; depositing a third layer on the separation layer; and removing a portion of the separation layer and the third layer from the substrate such that a substantially planar surface is formed exposing the first layer, the separation layer, and the third layer.

Abstract translation: 本发明涉及在衬底上形成一个或多个横向纳米结构的方法。 该方法包括以下步骤：提供衬底; 在衬底上沉积第一层; 在所述第一层上形成至少一个边缘; 在第一层上沉积至少一个分离层; 在分离层上沉积第三层; 以及从所述基板移除所述分离层和所述第三层的一部分，使得形成露出所述第一层，所述分离层和所述第三层的基本平坦的表面。

公开(公告)号：US11987493B2

公开(公告)日：2024-05-21

申请号：US17288250

申请日：2019-10-30

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Daiki Suzuki ,  Nao Inoue ,  Katsumi Shibayama

IPC: G02B26/08 ,  B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0072 ,  B81C1/00666 ,  G02B26/0833 ,  B81B2201/042 ,  B81B2207/07 ,  B81C2201/0104 ,  B81C2201/0181

Abstract: The damascene wiring structure includes a base including a main surface provided with a groove, an insulating layer including a first portion provided on an inner surface of the groove and a second portion provided on the main surface, a metal layer provided on the first portion, a wiring portion embedded in the groove, and a cap layer provided to cover the second portion, an end portion of the metal layer, and the wiring portion. A surface of a boundary part between the first portion and the second portion includes an inclined surface inclined with respect to a direction perpendicular to the main surface. The end portion of the metal layer enters between the cap layer and the inclined surface, and in the end portion, a first surface along the cap layer and a second surface along the inclined surface form an acute angle.

公开(公告)号：US20230382715A1

公开(公告)日：2023-11-30

申请号：US18324533

申请日：2023-05-26

Applicant: COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Samer DAGHER ,  Loïc JOET

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81C1/00158 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0361 ,  B81B2203/04 ,  B81B2207/11 ,  B81C2201/0133 ,  B81C2201/014 ,  B81C2201/0104

Abstract: An electroacoustic transducer includes a frame; an element movable relative to the frame, the movable element including a membrane; an internal cavity called back volume, subjected to a reference pressure and delimited by the movable element and walls belonging to the frame; in which transducer at least one of the walls delimiting the back volume includes at least one sealed cavity and in which a pressure lower than the reference pressure prevails in the at least one sealed cavity.

公开(公告)号：US20230302495A1

公开(公告)日：2023-09-28

申请号：US17993899

申请日：2022-11-24

Applicant: Zhejiang Xiansheng Technology Co., Ltd.

Inventor： Feng Yin ,  Hui Li

IPC: B06B1/02 ,  B81B7/00 ,  B81C1/00

CPC classification number: B06B1/0292 ,  B81B7/0006 ,  B81C1/00238 ,  B81B2201/0271 ,  B81B2203/0127 ,  B81B2203/04 ,  B81B2207/03 ,  B81B2207/07 ,  B81B2207/012 ,  B81C2201/0104 ,  B81C2203/036 ,  B81C2203/0792

Abstract: The present invention provides a new architecture of system-on-chip ultrasonic transducer array. It is based on fusion bond of two active wafers which have prefabricated CMOS integrated circuits and CMUT structures; precise thin-down of one wafer to form CMUT monocrystalline silicon membrane; and then to vertically connect CMUT array to CMOS IC layers underneath. This architecture can realize a high-density CMUT array with multiple layers of CMOS devices, such as all supporting CMOS ICs, to achieve a SOC solution. The present invention further provides a manufacturing method for above-mentioned SOC CMUT approach, and this manufacturing process can be realized in both 8 inch and 12-inch wafer manufacturing fabs. The disclosed manufacturing processes are more compatible with existing CMOS process flow, more cost-competitive for mass production.

公开(公告)号：US09932222B2

公开(公告)日：2018-04-03

申请号：US15162994

申请日：2016-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Brigham ,  Christopher V. Jahnes ,  Cameron E. Luce ,  Jeffrey C. Maling ,  William J. Murphy ,  Anthony K. Stamper ,  Eric J. White

IPC: B81C1/00 ,  G06F17/50 ,  B81B3/00

CPC classification number: B81C1/0015 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2207/09 ,  B81C1/00047 ,  B81C1/00269 ,  B81C1/00365 ,  B81C1/00531 ,  B81C1/00936 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0121 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0714 ,  G06F17/5009

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

公开(公告)号：US09731963B2

公开(公告)日：2017-08-15

申请号：US15265668

申请日：2016-09-14

Applicant: InvenSense, Inc.

Inventor： Cerina Zhang ,  Martin Lim ,  Jongwoo Shin ,  Joseph Seeger

IPC: H01L23/02 ,  B81C1/00 ,  B81B7/02 ,  B81B7/00

CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/0023 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00269 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792

Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.