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    Method and apparatus for micro electro-mechanical systems and their manufacture
    12.
    发明申请
    Method and apparatus for micro electro-mechanical systems and their manufacture 审中-公开
    微机电系统及其制造方法和装置

    公开(公告)号：US20020127760A1

    公开(公告)日：2002-09-12

    申请号：US09922590

    申请日：2001-08-02

    Inventor： Jer-Liang Yeh ,  Norman C. Tien

    IPC: H01L021/00

    CPC classification number: B81C1/00619 ,  B81B2203/0136 ,  B81C1/00182 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2201/056 ,  H04R19/005

    Abstract: The present invention provides a fabrication process that integrates high-aspect-ratio silicon structures with polysilicon surface micromachined structures. In some embodiments the process includes forming an oxide block by etching a plurality of trenches to leave a plurality of vertical-walled silicon structures standing on the substrate, thermally and substantially completely oxidizing the vertical-walled silicon structures, and substantially filling spaces between the oxidized vertical-walled silicon structures with an oxide of silicon to form the oxide block. The process retains not only the high-aspect-ratio silicon structures possible with deep reactive ion etching (DRIE) but also the design flexibility of polysilicon surface micromachining. Using this process, polysilicon platforms have been fabricated, which are actuated by high-aspect-ratio combdrives for many applications such as x-y-z stages and scanning devices. The actuators include an asymmetric combdrive that actuates in torsional/out-of-plane motions, and a high-aspect-ratio combdrive that drives in translational motion.

    Abstract translation: 本发明提供了一种将高纵横比硅结构与多晶硅表面微加工结构相集成的制造工艺。 在一些实施方案中，该方法包括通过蚀刻多个沟槽来形成氧化物块，以留下多个垂直壁硅结构站立在衬底上，热并基本上完全氧化垂直壁硅结构，并且基本上填充氧化的 具有硅氧化物的垂直壁硅结构以形成氧化物块。 该过程不仅保留了高纵横比的硅结构，而且可以通过深反应离子蚀刻（DRIE）进行，而且还保留了多晶硅表面微机械加工的设计灵活性。 使用这个过程，已经制造了多晶硅平台，其由用于诸如x-y-z级和扫描装置的许多应用的高纵横比梳齿驱动。 致动器包括在扭转/超平面运动中致动的非对称梳齿驱动器以及在平移运动中驱动的高纵横比梳齿驱动。

    Process for integrating dielectric optical coatings into micro-electromechanical devices
    13.
    发明申请
    Process for integrating dielectric optical coatings into micro-electromechanical devices 有权
    将介电光学涂层集成到微机电装置中的工艺

    公开(公告)号：US20020048839A1

    公开(公告)日：2002-04-25

    申请号：US09954861

    申请日：2001-09-18

    Applicant: AXSUN Technologies, Inc.

    Inventor： Michael F. Miller ,  Minh Van Le ,  Christopher C. Cook ,  Dale C. Flanders ,  Steven F. Nagle

    IPC: H01L021/00

    CPC classification number: B81B3/0083 ,  B81B2201/042 ,  B81B2201/047 ,  B81C1/0038 ,  B81C2201/0159 ,  B81C2201/053 ,  B81C2201/056 ,  G02B26/001

    Abstract: A process for patterning dielectric layers of the type typically found in optical coatings in the context of MEMS manufacturing is disclosed. A dielectric coating is deposited over a device layer, which has or will be released, and patterned using a mask layer. In one example, the coating is etched using the mask layer as a protection layer. In another example, a lift-off process is shown. The primary advantage of photolithographic patterning of the dielectric layers in optical MEMS devices is that higher levels of consistency can be achieved in fabrication, such as size, location, and residual material stress. Competing techniques such as shadow masking yield lower quality features and are difficult to align. Further, the minimum feature size that can be obtained with shadow masks is limited to null100 nullm, depending on the coating system geometry, and they require hard contact with the surface of the wafer, which can lead to damage and/or particulate contamination.

    Abstract translation: 公开了一种用于在MEMS制造的上下文中通常在光学涂层中发现的类型的介电层图案的工艺。 电介质涂层沉积在器件层上，器件层已经或将被释放，并使用掩模层进行图案化。 在一个实例中，使用掩模层作为保护层来蚀刻涂层。 在另一示例中，示出了剥离过程。 光学MEMS器件中电介质层的光刻图案的主要优点是可以在诸如尺寸，位置和残余材料应力的制造中实现更高水平的稠度。 诸如阴影掩蔽的竞争技术产生较低的质量特征并且难以对准。 此外，根据涂层系统的几何形状，使用荫罩可获得的最小特征尺寸限制在〜100μm，并且它们需要与晶片的表面硬接触，这可能导致损坏和/或微粒污染。

    MEMS DEVICE MANUFACTURING METHOD
    15.
    发明公开
    MEMS DEVICE MANUFACTURING METHOD 审中-公开

    公开(公告)号：US20230348262A1

    公开(公告)日：2023-11-02

    申请号：US18139973

    申请日：2023-04-27

    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

    Inventor： Audrey Berthelot ,  Philippe Robert

    IPC: B81C1/00

    CPC classification number: B81C1/00801 ,  B81C2201/0132 ,  B81C2201/056

    Abstract: The present description concerns a method of manufacturing a microelectromechanical device, including the following successive steps: providing an SOI structure comprising a first semiconductor layer on an insulating layer; forming a second semiconductor layer by epitaxy on top of and in contact with the upper surface of the first semiconductor layer; transferring and bonding, by molecular bonding, a third semiconductor layer onto and in contact with the upper surface of the second semiconductor layer; and forming trenches vertically extending from the upper surface of the third semiconductor layer all the way to the upper surface of the insulating layer, said trenches laterally delimiting a mechanical element of the device.

    Integrated MEMS device
    17.
    发明授权
    Integrated MEMS device 有权

    公开(公告)号：US09676609B2

    公开(公告)日：2017-06-13

    申请号：US15144896

    申请日：2016-05-03

    Applicant: Asia Pacific Microsystems, Inc.

    Inventor： Jerwei Hsieh

    IPC: H01L21/4763 ,  B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

    Abstract: An integrated MEMS device is provided. The integrated MEMS device comprises a circuit chip and a device chip. The circuit chip has a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials. The device chip has a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip. A plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.

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