公开(公告)号：US07846641B2

公开(公告)日：2010-12-07

申请号：US12143446

申请日：2008-06-20

Applicant: Ryohei Satoh ,  Koji Nakagawa ,  Reo Usui ,  Kenji Tanaka ,  Satoru Takaki ,  Kenichi Ebata ,  Yumiko Aoki

Inventor： Ryohei Satoh ,  Koji Nakagawa ,  Reo Usui ,  Kenji Tanaka ,  Satoru Takaki ,  Kenichi Ebata ,  Yumiko Aoki

IPC: G03F7/26

CPC classification number: H05K3/28 ,  H01J9/02 ,  H01J11/12 ,  H01J11/34 ,  H05K1/0306 ,  H05K3/027 ,  H05K3/38 ,  H05K2201/0269 ,  Y10T428/24868

Abstract: A process for producing a glass substrate having a circuit pattern is disclosed. The process includes forming a thin film layer on a glass substrate and then irradiating the thin film layer with laser light to form a circuit pattern on the glass substrate; depositing a low-melting point glass having a softening point of from 450 to 630° C. on the glass substrate having the circuit pattern formed thereon; and sintering the low-melting point glass to form a low-melting point glass layer which includes the low-melting point glass sintered on the glass substrate having the circuit pattern formed thereon and which forms a compatible layer between the glass substrate and the low-melting point glass layer.

Abstract translation: 公开了一种具有电路图案的玻璃基板的制造方法。 该方法包括在玻璃基板上形成薄膜层，然后用激光照射薄膜层，以在玻璃基板上形成电路图案; 在其上形成有电路图案的玻璃基板上沉积软化点为450〜630℃的低熔点玻璃; 并烧结低熔点玻璃以形成低熔点玻璃层，该低熔点玻璃层包括在其上形成有电路图案的玻璃基板上烧结的低熔点玻璃，并且在玻璃基板和低熔点玻璃之间形成相容层， 熔点玻璃层。

公开(公告)号：US07691469B2

公开(公告)日：2010-04-06

申请号：US12049848

申请日：2008-03-17

Applicant: Masato Nomiya

Inventor： Masato Nomiya

IPC: B32B9/00

CPC classification number: H05K3/38 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0195 ,  H05K2201/0269 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/24942

Abstract: A ceramic multilayer substrate exhibiting reduced pealing and breakage of an internal conductor disposed between a ceramic layer serving as a base member and a ceramic layer for restricting shrinkage includes a first ceramic layer 11, a second ceramic layer 12 laminated so as to come into contact with a principal surface of the first ceramic layer 11, and an internal conductor 13 disposed between the first ceramic layer 11 and the second ceramic layer 12, a phosphorus component layer 16a is disposed in the first ceramic layer 11 with a concentration gradient in which the concentration decreases in a direction away from the internal conductor 13.

Abstract translation: 表现出设置在用作基底的陶瓷层和用于限制收缩的陶瓷层之间的内部导体的减小的剥离和断裂的陶瓷多层基板包括层叠以与第二陶瓷层12接触的第一陶瓷层11，第二陶瓷层12 第一陶瓷层11的主表面和设置在第一陶瓷层11和第二陶瓷层12之间的内部导体13，在第一陶瓷层11中设置磷成分层16a，浓度梯度为浓度梯度， 在远离内部导体13的方向上减小。

公开(公告)号：US20100032190A1

公开(公告)日：2010-02-11

申请号：US12535760

申请日：2009-08-05

Applicant: Atsushi YAMAGUCHI ,  Koso MATSUNO ,  Ryo KUWABARA ,  Hiroe KOWADA ,  Kimiaki NAKAYA

Inventor： Atsushi YAMAGUCHI ,  Koso MATSUNO ,  Ryo KUWABARA ,  Hiroe KOWADA ,  Kimiaki NAKAYA

IPC: H05K7/20

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/75 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/0203 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T428/24372 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A mounting structure formed by bonding the electrodes of a substantially planar electronic component to the electrodes provided on the mounting surface of a circuit board includes a sealing body 5 formed between one main surface of the electronic component and the circuit board and/or on the other main surface of the electronic component. The sealing body 5 is composed of a plurality of layers having different adhesive strengths and thermal conductivities, wherein a layer having a relatively high adhesion strength is arranged in a region being in contact with either one of the electronic component and the circuit board, and a layer having a relatively high thermal conductivity is arranged in a region being in contact with none of the electronic component and the circuit board.

Abstract translation: 通过将基本上平面的电子部件的电极接合到设置在电路基板的安装面上的电极而形成的安装结构包括形成在电子部件的一个主面和电路基板之间和/或另一个之间的密封体5 电子元件的主表面。 密封体5由具有不同粘合强度和导热性的多个层组成，其中具有相对较高粘合强度的层被布置在与电子部件和电路板中的任一个接触的区域中，并且 在与电子部件和电路基板没有接触的区域中布置具有较高热传导率的层。

公开(公告)号：US06899960B2

公开(公告)日：2005-05-31

申请号：US10104830

申请日：2002-03-22

Applicant: Song-Hua Shi ,  Lejun Wang ,  Tian-An Chen

Inventor： Song-Hua Shi ,  Lejun Wang ,  Tian-An Chen

IPC: B32B27/08 ,  C09J161/34 ,  C09J179/04 ,  H01B3/30 ,  H01B3/38 ,  H01L21/56 ,  H01L23/29

CPC classification number: C08G73/02 ,  B32B27/08 ,  C08L79/02 ,  C09J161/34 ,  C09J179/04 ,  H01B3/303 ,  H01B3/38 ,  H01L21/563 ,  H01L23/293 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K3/323 ,  H05K2201/0269 ,  Y10T428/12528 ,  Y10T428/31511 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: Microelectronic and optoelectronic packaging embodiments are described with underfill materials including polybenzoxazine, having the general formula:

Abstract translation: 使用具有以下通式的聚苯并恶嗪的底部填充材料描述微电子和光电子封装实施例：

公开(公告)号：US20240206061A1

公开(公告)日：2024-06-20

申请号：US18537877

申请日：2023-12-13

Applicant: IBIDEN CO., LTD.

Inventor： Ryo ANDO ,  Nobuhisa KURODA ,  Shogo FUKUI ,  Kosei ICHIKAWA ,  Makoto KATO

IPC: H05K1/03 ,  H05K1/02

CPC classification number: H05K1/0373 ,  H05K1/0298 ,  H05K2201/0209 ,  H05K2201/0254 ,  H05K2201/0269

Abstract: A wiring substrate includes an insulating layer including a first layer and a second layer, and a conductor layer including a metal film formed on a surface of the second layer of the insulating layer such that the conductor layer includes a conductor pattern. The first layer includes resin and first inorganic particles, the second layer includes resin and second inorganic particles at the content rate that is lower than the content rate of the first inorganic particles in the first layer, and the thickness of the first layer is 90% or more of the thickness of the insulating layer. The second layer of the insulating layer includes a composite layer having the thickness in the range of 0.1 to 0.3 μm, and the composite layer includes part of the metal film in the conductor layer formed in gaps between the second inorganic particles and resin in the second layer.

公开(公告)号：US09918381B2

公开(公告)日：2018-03-13

申请号：US14588614

申请日：2015-01-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoru Noda

IPC: H05K1/18 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H05K3/28 ,  H05K3/46 ,  H05K1/03 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K1/0271 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/3511 ,  H05K1/036 ,  H05K1/0373 ,  H05K1/186 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/0347 ,  H05K2201/09136 ,  H05K2201/10636 ,  H05K2203/0126 ,  H05K2203/0465 ,  H05K2203/085 ,  H05K2203/1316 ,  H05K2203/1322 ,  Y02P70/611

Abstract: A component-embedded substrate includes a substrate portion, an embedded electronic component, and a resin portion. The substrate portion has inner electrodes on an inner principal surface. The embedded electronic component has terminal electrodes and is mounted to the substrate portion via solder fillets adhering to the respective terminal electrodes and the respective inner electrodes. The resin portion is stacked on the substrate portion, with the embedded electronic component embedded therein. The resin portion includes a no-filler-added layer and a filler-added layer. The no-filler-added layer extends from the inner principal surface to a height which allows at least the solder fillets to be covered. The filler-added layer contains an inorganic filler and extends from an interface with the no-filler-added layer to a height which allows at least the embedded electronic component to be covered.

公开(公告)号：US20170347449A1

公开(公告)日：2017-11-30

申请号：US15536954

申请日：2015-12-18

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Motohiko SUGIURA ,  Takashi KASUGA ,  Yoshio OKA ,  Shigeaki UEMURA ,  Jinjoo PARK ,  Hiroshi UEDA ,  Kousuke MIURA

IPC: H05K1/09 ,  H05K3/24 ,  H05K1/03 ,  H05K1/02 ,  H05K3/38 ,  H05K1/05 ,  B82Y30/00

CPC classification number: H05K1/097 ,  B82Y30/00 ,  B82Y40/00 ,  H05K1/0298 ,  H05K1/03 ,  H05K1/05 ,  H05K1/09 ,  H05K3/24 ,  H05K3/38 ,  H05K3/388 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0266 ,  H05K2201/0269

Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film having an insulating property, and a metal layer formed on at least one surface side of the base film. In the substrate for a printed circuit board, a plurality of fine particles are disposed between the base film and the metal layer, and the fine particles are formed of a metal the same as a main metal of the metal layer or formed of a metal compound of the main metal. The fine particles preferably have an average particle size of 0.1 nm or more and 20 nm or less. The fine particles are preferably formed of a metal oxide or a metal hydroxide. The fine particles are preferably present between the base film and the metal layer so as to form a layer. The metal layer preferably includes a metal grain layer formed by firing metal nanoparticles.

公开(公告)号：US09423691B2

公开(公告)日：2016-08-23

申请号：US14658684

申请日：2015-03-16

Applicant: TAIYO HOLDINGS CO., LTD.

Inventor： Takahiro Yoshida ,  Shouji Minegishi ,  Masao Arima

IPC: G03F7/004 ,  G03F7/095 ,  H05K3/28

CPC classification number: G03F7/095 ,  G03F7/004 ,  G03F7/0047 ,  H05K3/285 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068

Abstract: In a layered structure having at least a substrate and a photosensitive resin layer or cured film layer formed on the substrate and containing an inorganic filler, the content of the inorganic filler in the photosensitive resin layer or cured film layer is low on the side contacting the substrate and high on the surface side away from the substrate, so that a linear thermal expansion coefficient of the photosensitive resin layer or cured film layer as a whole is maintained as low as possible. Preferably, the inorganic filler content in the layer gradually increases continuously obliquely or stepwise from the side contacting the substrate to the surface side away from the substrate. A photosensitive dry film containing the above-mentioned photosensitive resin layer is suitable for use as a solder resist or an interlayer resin insulation layer of a printed wiring board.

公开(公告)号：US20160047767A1

公开(公告)日：2016-02-18

申请号：US14460598

申请日：2014-08-15

Applicant: John Andrew Lebens ,  Ronald Steven Cok ,  Yongcal Wang

Inventor： John Andrew Lebens ,  Ronald Steven Cok ,  Yongcal Wang

IPC: G01N27/12

CPC classification number: G01N27/126 ,  G01N27/07 ,  G02F1/13439 ,  G06F3/044 ,  G06F2203/04103 ,  H05K3/0014 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/0112 ,  H05K2201/0257 ,  H05K2201/0269 ,  H05K2201/0272 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/2054 ,  H05K2203/0108 ,  H05K2203/1131 ,  H05K2203/1476

Abstract: A method of operating an imprinted electronic sensor to sense an environmental factor includes providing spatially separated micro-channels in a cured layer on a substrate. A multi-layer micro-wire is formed in each micro-channel. Each multi-layer micro-wire includes at least a conductive layer and a reactive layer exposed to the environmental factor. The conductive layer is a cured electrical conductor located only within the micro-channel and at least a portion of the reactive layer responds to the environmental factor. A controller is provided for electrically controlling first and second groups of multi-layer micro-wires, each first and second group including one or more multi-layer micro-wires. The reactive layer is exposed to the environment. The controller measures the electrical response of the first and second groups of multi-layer micro-wires. The electrical response includes at least one of the amperometric response, the resistance, the capacitance, the impedance, the complex impedance, or the inductance.

Abstract translation: 操作印刷电子传感器以感测环境因素的方法包括在基板上的固化层中提供空间分离的微通道。 在每个微通道中形成多层微线。 每个多层微线包括至少暴露于环境因素的导电层和反应层。 导电层是仅位于微通道内的固化电导体，并且反应层的至少一部分响应于环境因素。 提供一种用于电控制第一组和第二组多层微线的控制器，每个第一组和第二组包括一个或多个多层微线。 反应层暴露于环境中。 控制器测量第一组和第二组多层微线的电响应。 电响应包括电流响应，电阻，电容，阻抗，复阻抗或电感中的至少一个。

公开(公告)号：US09161444B2

公开(公告)日：2015-10-13

申请号：US14354600

申请日：2012-09-28

Applicant: KYOCERA Corporation

Inventor： Kiyotaka Nakamura ,  Yoshio Ohashi ,  Kunihide Shikata

IPC: H05K1/00 ,  H05K1/09 ,  H05K3/38 ,  H01L23/15 ,  C04B41/90 ,  C04B41/00 ,  C04B41/52 ,  H05K1/03 ,  H01L23/373 ,  C04B111/00

CPC classification number: H05K1/09 ,  C04B41/009 ,  C04B41/52 ,  C04B41/90 ,  C04B2111/00405 ,  C04B2111/00844 ,  H01L23/15 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/3736 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/245 ,  H05K3/38 ,  H05K2201/0269 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2203/1126 ,  C04B35/00 ,  C04B35/10 ,  C04B35/185 ,  C04B35/48 ,  C04B35/581 ,  C04B35/584 ,  C04B41/4539 ,  C04B41/4572 ,  C04B41/5022 ,  C04B41/5127 ,  C04B41/5116 ,  C04B41/522 ,  C04B41/5155 ,  H01L2924/00

Abstract: A circuit board is provided with a metal wiring layer 12 on at least one principal surface of a ceramic sintered body 11, wherein the above-described metal wiring layer includes a first region 12a which is in contact with the principal surface and which contains a glass component and a second region 12b which is located on the first region 12a and which does not contain a glass component, the thickness of the first region 12a is 35% or more and 70% or less of the thickness of the metal wiring layer 12, and the average grain size in the first region 12a is smaller than the average grain size in the second region 12b.

Abstract translation: 电路板在陶瓷烧结体11的至少一个主面上设置有金属布线层12，其中上述金属布线层包括与主表面接触且包含玻璃的第一区域12a 第一区域12a和第二区域12b位于第一区域12a上并且不包含玻璃成分，第一区域12a的厚度为金属布线层12的厚度的35％以上且70％以下， 并且第一区域12a中的平均晶粒尺寸小于第二区域12b中的平均晶粒尺寸。