公开(公告)号：US20070244684A1

公开(公告)日：2007-10-18

申请号：US11405242

申请日：2006-04-17

Applicant: Rajen Murugan ,  Jimmy Pike ,  Abeye Teshome

Inventor： Rajen Murugan ,  Jimmy Pike ,  Abeye Teshome

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  H05K1/0216 ,  H05K1/0237 ,  H05K3/0005 ,  H05K3/429 ,  H05K2201/09327

Abstract: A methodology may be used that takes into account the inductive coupling of current transients on the power rails of a printed circuit board (PCB) that may be coupled to the barrel of a via. By taking into account the coupling of the current transients on the power rails of the PCB, more accurate and realistic modeling results may be obtained. Inductive coupling of the current transients from the power rails may be more pronounced at higher frequencies and may be additive for more layer transitions (e.g., more via transitions) of the PCB.

Abstract translation: 可以使用考虑到可以耦合到通孔的筒的印刷电路板（PCB）的电源轨上的电流瞬变的电感耦合的方法。 通过考虑PCB上电源线上的电流瞬变的耦合，可以获得更精确和逼真的建模结果。 来自电源轨的电流瞬变的感性耦合可能在较高频率下更为显着，并且可能对于PCB的更多层转变（例如更多的经由转变）而言是相加的。

公开(公告)号：US20070109726A1

公开(公告)日：2007-05-17

申请号：US11281688

申请日：2005-11-17

Applicant: Wiren Becker ,  Bruce Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

Inventor： Wiren Becker ,  Bruce Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

IPC: H02B1/00

CPC classification number: H05K1/0262 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663

Abstract: The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.

Abstract translation: 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各个平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

公开(公告)号：US20060256540A1

公开(公告)日：2006-11-16

申请号：US11414548

申请日：2006-05-01

Applicant: Shadi AbuGhazaleh ,  Robert Baxter ,  Rehan Mahmood ,  Alan Miller ,  Michael O'Connor

Inventor： Shadi AbuGhazaleh ,  Robert Baxter ,  Rehan Mahmood ,  Alan Miller ,  Michael O'Connor

IPC: H05K7/06 ,  H05K7/10

CPC classification number: H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/0723 ,  H05K2201/09327 ,  H05K2201/10189 ,  H05K2201/10689 ,  Y10S439/941

Abstract: A compensating advanced feature patch panel that can include removable modular or fixed electronic components located directly on the patch panel which are separately or in combination capable of providing advanced features such as device detection and power insertion. The patch panel provides communications between an insulation displacement connector (IDC) at a PD/User end, and any standard interface type using unshielded twisted pair cables, such as an RJ45 connector at a switch end at performance levels of at least category 3, 5, 6e, 6 and/or higher (e.g. 6e or 7) and equivalent performance levels by compensating for the active electronics used in providing advanced features. Compensation is achieved in part through the separation and isolation of active and communication circuit elements.

Abstract translation: 补偿高级功能接线板，其可以包括直接位于接线板上的可拆卸模块或固定电子部件，其分开地或组合地能够提供诸如设备检测和功率插入的高级特征。 接线板提供PD /用户端的绝缘位移连接器（IDC）与使用非屏蔽双绞线电缆的任何标准接口类型之间的通信，例如在开关端的RJ45连接器，性能水平至少为3,5 ，6e，6和/或更高（例如6e或7）和等效的性能水平，通过补偿用于提供高级功能的有源电子元件。 补偿部分通过主动和通信电路元件的分离和隔离来实现。

公开(公告)号：US20060076668A1

公开(公告)日：2006-04-13

申请号：US11244333

申请日：2005-10-06

Applicant: Sung-ki Kim

Inventor： Sung-ki Kim

IPC: H01L23/52 ,  H05K7/06

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09327

Abstract: A multi-layer PCB includes a first signal layer, a ground layer, a second signal layer, a third signal layer, an electric power layer, and a fourth signal layer, including a first insulating layer arranged between the first signal layer and the ground layer; a second insulating layer arranged between the ground layer and the second signal layer; a third insulating layer arranged between the second signal layer and the third signal layer; a fourth insulating layer arranged between the third signal layer and the electric power layer; and a fifth insulating layer arranged between the electric power layer and the fourth signal layer, wherein at least one of the first signal layer, the second signal layer, the third signal layer, and the fourth signal layer includes a pattern.

Abstract translation: 多层PCB包括第一信号层，接地层，第二信号层，第三信号层，电力层和第四信号层，包括布置在第一信号层和地之间的第一绝缘层 层; 布置在所述接地层和所述第二信号层之间的第二绝缘层; 布置在所述第二信号层和所述第三信号层之间的第三绝缘层; 布置在所述第三信号层和所述电力层之间的第四绝缘层; 以及布置在所述电力层和所述第四信号层之间的第五绝缘层，其中所述第一信号层，所述第二信号层，所述第三信号层和所述第四信号层中的至少一个包括图案。

公开(公告)号：US20060003612A1

公开(公告)日：2006-01-05

申请号：US10884330

申请日：2004-07-02

Applicant: David Spengler

Inventor： David Spengler

IPC: H01R13/648

CPC classification number: G06F1/189 ,  G06F1/187 ,  H01R13/6471 ,  H05K1/0216 ,  H05K2201/09327

Abstract: An electronics cabinet is provided comprising an electrical connector in electrical communication with a printed circuit board (PCB) comprising a PCB power plane, the connector comprising a plurality of power contacts defining a connector power plane adapted for receiving a substantially even power load distribution from the PCB power plane among the power contacts.

公开(公告)号：US20050225955A1

公开(公告)日：2005-10-13

申请号：US10821458

申请日：2004-04-09

Applicant: John Grebenkemper ,  Frank Mikalauskas ,  Srinivasan Venkataraman ,  Jonathan Buck

Inventor： John Grebenkemper ,  Frank Mikalauskas ,  Srinivasan Venkataraman ,  Jonathan Buck

IPC: G01S13/00 ,  H05K1/00 ,  H05K1/02 ,  H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0218 ,  H05K1/0298 ,  H05K2201/0723 ,  H05K2201/09309 ,  H05K2201/09327

Abstract: A printed circuit board includes a power plane and a ground reference plane that includes two opposite sides. The power plane is positioned proximate one side of the ground reference plane. A signal layer is positioned proximate the other side of the ground reference plane to isolate the power plane from the signal layer. Any noise on the power plane or the signal layer is thus isolated by the intervening ground plane.

Abstract translation: 印刷电路板包括电源平面和包括两个相对侧的接地参考平面。 电源平面位于接地参考平面的一侧。 信号层位于接地参考平面的另一侧附近，以将功率平面与信号层隔离。 电力平面或信号层上的任何噪声因此被插入的接地层隔离。

公开(公告)号：US06384340B1

公开(公告)日：2002-05-07

申请号：US09800408

申请日：2001-03-06

Applicant: Yu-Chiang Cheng

Inventor： Yu-Chiang Cheng

IPC: H05K103

CPC classification number: H05K1/024 ,  H05K1/0298 ,  H05K3/4688 ,  H05K2201/0145 ,  H05K2201/0191 ,  H05K2201/09327

Abstract: A multi-layer circuit board includes first, second, third, fourth and fifth insulating substrates, first, second, third and fourth signal wiring layers, a ground wiring layer, and a power wiring layer. The insulating substrates and the wiring layers are press-bonded to each other to form the circuit board with a thickness of about 1.2 mm. Each of the first and fifth insulating substrates has a thickness ranging from 4.175 to 4.725 mil. Each of the second and fourth insulating substrates has a thickness ranging from 5.7 to 6.3 mil. The third insulating substrate has a thickness ranging to 16.8 mil.

Abstract translation: 多层电路板包括第一，第二，第三，第四和第五绝缘基板，第一，第二，第三和第四信号布线层，接地布线层和电源布线层。 绝缘基板和布线层彼此压接，形成约1.2mm厚度的电路板。 第一和第五绝缘基板中的每一个的厚度范围为4.175至4.725密耳。 第二绝缘基板和第四绝缘基板中的每一个具有5.7至6.3密耳的厚度。 第三绝缘基板的厚度为16.8密耳。

公开(公告)号：US5912809A

公开(公告)日：1999-06-15

申请号：US786581

申请日：1997-01-21

Applicant: Todd W. Steigerwald ,  Leroy Jones

Inventor： Todd W. Steigerwald ,  Leroy Jones

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H05K1/11

CPC classification number: H05K1/0262 ,  H05K1/162 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09327

Abstract: Electrical potentials and very high frequency (VHF) currents in a circuit board are controlled by patterning the power plane of a multiple layered, capacitive plane printed circuit board in selected geometric patterns. The selected geometric patterns, both simple and complex, control voltages and currents by channeling the capacitance capacity for usage directed to a particular integrated circuit or circuits, isolated to a particular integrated circuit or circuits, or shared between integrated circuits. Accordingly, the capacitive planes including the geometrically patterned power plane are channeled capacitive planes (CCP) that are formed on multiple layers of a single printed circuit board to support flexible, three-dimensional control of VHF electrical currents.

Abstract translation: 电路板中的电位和非常高频（VHF）电流通过以选定的几何图形图案化多层电容平面印刷电路板的功率平面来控制。 所选择的几何图形，简单和复杂，通过引导电容容量来控制电压和电流，用于指向特定集成电路或隔离到特定集成电路或电路的集成电路或集成电路之间共享的电路。 因此，包括几何图案化的功率平面的电容平面是形成在单个印刷电路板的多层上的通道电容平面（CCP），以支持VHF电流的灵活的三维控制。

公开(公告)号：US5436062A

公开(公告)日：1995-07-25

申请号：US193191

申请日：1994-02-14

Applicant: Walter Schmidt ,  Marco Martinelli

Inventor： Walter Schmidt ,  Marco Martinelli

IPC: H05K1/00 ,  H05K1/05 ,  H05K1/11 ,  H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  B44C1/22 ,  B32B3/00 ,  C23F1/02

CPC classification number: H05K3/4655 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/4084 ,  H05K3/42 ,  H05K3/4635 ,  H05K3/4641 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09572 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  Y10S428/901 ,  Y10T428/24917

Abstract: In a metal-clad laminate the requirements concerning the mechanical strength are functionally separated from the circuit connection requirement, so as to be able to bring the circuit connection, particularly for signals, "closer" to the electrotechnical characteristics of the chips. For this purpose and without taking account of the mechanical strength of the substrate, the layout miniaturization is optimized. In place of a circuit board (MCM), a laminate which can be built up to a circuit board is produced. The inventive laminate comprises an extremely thin foil with a plurality of extremely small holes simultaneously etched in an etching process. The hole diameter can be reduced by almost an order of magnitude (up to 20 .mu.m), which permits a sub-100 .mu.m technology. Such a laminate is not used as a mechanical support and is only provided for signal guidance. The effect of the miniaturization can be seen in the diameter for the plated-through holes. With a hole diameter reduction there is an increase in the current path density, which gives over 10000 plated-through holes per dm.sup.2. A drawing shows the compression ratio compared with standard technology.

Abstract translation: PCT No.PCT / CH93 / 00145 Sec。 371日期1994年2月14日 102（e）1994年2月14日PCT PCT 1993年6月9日PCT公布。 公开号WO93 / 26143 日期为1993年12月23日。在覆金属层压板中，关于机械强度的要求在功能上与电路连接要求分离，以便能够使电路连接，特别是对于信号，“更接近”电工特性 的芯片。 为此，不考虑基板的机械强度，优化了布局小型化。 代替电路板（MCM），可以生产可构建到电路板的层压板。 本发明的层压板包括在蚀刻工艺中同时蚀刻的具有多个极小孔的极薄箔。 孔径可以减少几乎一个数量级（高达20微米），这允许小于100微米的技术。 这种层压体不用作机械支撑，并且仅用于信号引导。 电镀通孔的直径可以看出小型化的效果。 随着孔径减小，电流通道密度增加，每dm2提供超过10000个电镀通孔。 图表显示了与标准技术相比的压缩比。

公开(公告)号：US4884170A

公开(公告)日：1989-11-28

申请号：US484891

申请日：1983-04-14

Applicant: Nobuaki Ohki ,  Norio Sengoku ,  Fumiyuki Kobayashi

Inventor： Nobuaki Ohki ,  Norio Sengoku ,  Fumiyuki Kobayashi

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K3/4623 ,  H05K1/024 ,  H05K2201/0158 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2203/061

Abstract: A multilayer printed circuit board having a plurality of printed circuit boards each having opposite surfaces respectively provided with an electric source or ground layer and a signal circuit layer. The plurality of printed circuit boards is stacked through adhesive layers such that the electric source or ground layer and the signal circuit layer are alternately disposed, the characteristic impedance of each signal circuit layer is given by a thickness and material of each of the substrate and the adhesive sheet disposed between the signal circuit layer and one of two electric source or ground layers adjacent to the signal circuit layer and between the same signal circuit layer and the other electric source or ground layer.

Abstract translation: 一种具有多个印刷电路板的多层印刷电路板，每个印刷电路板具有分别设置有电源或接地层的相对表面和信号电路层。 多个印刷电路板通过粘合层堆叠，使得电源或接地层和信号电路层交替布置，每个信号电路层的特性阻抗由每个基板的厚度和材料给出 粘合片设置在信号电路层和与信号电路层相邻并且在相同的信号电路层和另一个电源或接地层之间的两个电源或接地层中的一个之间。