公开(公告)号：US20140318758A1

公开(公告)日：2014-10-30

申请号：US14038837

申请日：2013-09-27

Applicant: Toyota Motor Engineering & Manufactruing North America, Inc.

Inventor： Ercan Mehmet Dede ,  Tsuyoshi Nomura ,  Paul Schmalenberg ,  Jae Seung Lee

IPC: F28F3/00

CPC classification number: H05K1/0203 ,  H05K1/0209 ,  H05K2201/0376 ,  H05K2201/09718 ,  H05K2201/09972 ,  H05K2201/10553

Abstract: Heat transfer management apparatuses according to the present disclosure includes a composite lamina having an insulator substrate and a thermal conductor at least partially embedded in the insulator substrate, a temperature-sensitive component coupled to the composite lamina, and a temperature-insensitive component coupled to the composite lamina and positioned distally from the temperature-sensitive component. The temperature-insensitive component produces heat during operation. The thermal conductor and the insulator substrate are arranged into a targeted heat transfer region proximate to the temperature-sensitive component and a bulk region proximate to the temperature-insensitive component. The targeted heat transfer region and the bulk region are in thermal continuity with one another.

Abstract translation: 根据本公开的热传递管理装置包括具有绝缘体衬底和至少部分地嵌入绝缘体衬底中的热导体的复合层，耦合到复合层的温度敏感组件和耦合到复合层的温度不敏感组件 复合层板，并远离温度敏感部件。 温度不敏感的部件在运行过程中产生热量。 热导体和绝缘体基板被布置成靠近温度敏感部件的目标传热区域和靠近温度不敏感部件的主体区域。 目标传热区域和体积区域彼此热连续。

公开(公告)号：US20140196941A1

公开(公告)日：2014-07-17

申请号：US13742168

申请日：2013-01-15

Applicant: FUJITSU LIMITED

Inventor： Yasuo Hidaka ,  Pradip Thachile

IPC: H05K1/11 ,  G06F17/50

CPC classification number: H05K1/116 ,  G06F17/50 ,  G06F17/5077 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0253 ,  H05K2201/09718 ,  H05K2201/09727 ,  Y10T29/49165

Abstract: The present disclosure relates to a method of optimizing via cutouts, including selecting a geometry of a via cutout on a first ground reference layer adjacent to a first differential trace, the geometry selected to provide an extension region extending in the direction of the first differential trace. Additionally, the method includes the steps of selecting a geometry of the first differential trace, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region, and selecting a radial dimension of a first and second via cutout on a second ground reference layer adjacent to and between the first and second differential traces, the radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

Abstract translation: 本公开涉及一种优化通孔切口的方法，包括选择与第一差分迹线相邻的第一接地参考层上的通路切口的几何形状，所述几何形状被选择以提供在第一差分迹线的方向上延伸的延伸区域 。 另外，该方法包括以下步骤：选择第一差分迹线的几何形状，其中延伸区域中的第一差分迹线的间隔与延伸区域外部的第一差分迹线的间隔不同，并且选择径向尺寸 在与第一和第二差分迹线相邻并且在第一和第二差分迹线之间的第二接地参考层上的第一和第二通孔切口，选择第一通孔切口和第二通孔切口的径向尺寸，使得第二接地参考层在相邻的区域中保持完整 第二个差分迹线。

公开(公告)号：US20140182891A1

公开(公告)日：2014-07-03

申请号：US14092039

申请日：2013-11-27

Applicant: Madhumitha Rengarajan ,  Jan De Geest ,  Stephen B. Smith ,  Stefaan Hendrik Jozef Sercu

Inventor： Madhumitha Rengarajan ,  Jan De Geest ,  Stephen B. Smith ,  Stefaan Hendrik Jozef Sercu

IPC: H05K1/02

CPC classification number: H05K1/116 ,  H05K1/0222 ,  H05K1/0251 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2203/0207 ,  H05K2203/0242

Abstract: In accordance with the various embodiments disclosed herein, an improved electrical connector footprint, such as on printed circuit boards (PCB), is described. For example, antipads can have a variety of sizes and pairs of differential signal traces can define centerlines that are spaced apart from each other.

Abstract translation: 根据本文公开的各种实施例，描述了改进的电连接器占用面积，例如在印刷电路板（PCB）上。 例如，反码器可以具有各种尺寸，并且差分信号迹线对可以定义彼此间隔开的中心线。

公开(公告)号：US20140033146A1

公开(公告)日：2014-01-30

申请号：US14042908

申请日：2013-10-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

公开(公告)号：US08586476B2

公开(公告)日：2013-11-19

申请号：US12874397

申请日：2010-09-02

Applicant: Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

Inventor： Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

IPC: H01L21/44

CPC classification number: H01L21/768 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/49165

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract translation: 电路基板使用后馈电顶部电源连接来提供改进的布线灵活性和较低的电源电压降/功率损耗。 在基板的外边缘附近使用电镀通孔，以提供与作为电源平面的管芯相邻的基板的顶部金属层的电源连接。 引脚插入通过电镀通孔以进一步降低电源路径的电阻。 引脚的底端可以延伸越过基板的底部以提供用于电源连接的可焊接互连，或者引脚的底端可以被焊接到基板的底部金属层上的“点动”电路图案，其连接 引脚连接到包括基板的集成电路封装的一个或多个电源端子。

公开(公告)号：US08471649B2

公开(公告)日：2013-06-25

申请号：US12376738

申请日：2007-09-07

Applicant: Jeff Devereux ,  Fritz Gerd Berger ,  William A. Johnston ,  Mohammad Ali Tassoudji ,  Scott Aldern

Inventor： Jeff Devereux ,  Fritz Gerd Berger ,  William A. Johnston ,  Mohammad Ali Tassoudji ,  Scott Aldern

IPC: H01P3/08 ,  H01P5/12

CPC classification number: H01P5/085 ,  H05K1/0243 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09718 ,  H05K2201/09809 ,  Y10T29/49139

Abstract: A compact Ku band microwave diplexer configured as a three port surface mount component on a miniature alumina substrate. Input signals occurring at a common port having frequencies within a first pass band are passed to a second port while being isolated from signals occurring at a third port. Signals occurring at the third port are passed to the common port while being isolated from the signals at the second port. A microstrip dual spur line filter is used combined with open circuit stubs to provide enhanced second harmonic suppression on the transmit side, while using a coupled line microstrip filter on the receive side. This approach allows for compact size and automated component assembly through pick and place and reflow manufacturing techniques.

Abstract translation: 在微型氧化铝基板上构造为三端口表面安装部件的紧凑型Ku波段微波双工器。 在具有第一通带内的频率的公共端口处发生的输入信号被传递到第二端口，同时与在第三端口处发生的信号隔离。 在第三个端口发生的信号被传递到公共端口，同时与第二个端口的信号隔​​离。 微带双支路线路滤波器与开路短路结合使用，以在接收侧使用耦合线路微带滤波器，在发射侧提供增强的二次谐波抑制。 这种方法允许通过拾取和放置和回流制​​造技术实现紧凑的尺寸和自动部件组装。

公开(公告)号：US08471153B2

公开(公告)日：2013-06-25

申请号：US12186604

申请日：2008-08-06

Applicant: Hironori Tanaka ,  Keisuke Shimizu

Inventor： Hironori Tanaka ,  Keisuke Shimizu

IPC: H05K1/16 ,  H05K1/18

CPC classification number: H05K1/162 ,  H05K1/09 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/4913

Abstract: A multilayer printed wiring board includes a core substrate, a resin insulation layer laminated on the core substrate and a capacitor section coupled to the resin insulating layer. The capacitor section includes a first electrode including a first metal and configured to be charged by a negative charge, and a second electrode including a second metal and opposing the first electrode, the second electrode configured to be charged by a positive charge. A dielectric layer is interposed between the first electrode and second electrode, and an ionization tendency of the first metal is larger than and ionization tendency of the second metal.

Abstract translation: 多层印刷线路板包括芯基板，层叠在芯基板上的树脂绝缘层和耦合到树脂绝缘层的电容器部分。 电容器部分包括第一电极，其包括第一金属并被构造为通过负电荷充电;以及第二电极，包括第二金属并与第一电极相对，第二电极被配置为通过正电荷充电。 电介质层插入在第一电极和第二电极之间，第一金属的电离倾向大于第二金属的离子化倾向。

公开(公告)号：US20130112468A1

公开(公告)日：2013-05-09

申请号：US13553414

申请日：2012-07-19

Applicant: Thomas S. COHEN ,  Marc B. Cartier, JR. ,  Mark W. Gailus

Inventor： Thomas S. COHEN ,  Marc B. Cartier, JR. ,  Mark W. Gailus

IPC: H05K1/11

CPC classification number: H01R13/646 ,  H01R13/514 ,  H01R13/6471 ,  H01R13/6587 ,  H01R23/688 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/115 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K7/1445 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

公开(公告)号：US20130011972A1

公开(公告)日：2013-01-10

申请号：US13618280

申请日：2012-09-14

Applicant: Martin Standing

Inventor： Martin Standing

IPC: H01L21/50

CPC classification number: H05K1/185 ,  H01L21/4846 ,  H01L23/3107 ,  H01L23/5389 ,  H01L25/072 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H05K1/16 ,  H05K3/429 ,  H05K2201/09718 ,  H05K2201/10643 ,  H01L2924/00

Abstract: A method of producing a laminate insert package includes providing a first metal layer, printing a first dielectric layer on the first metal layer, providing a second metal layer, printing a second dielectric layer on the second metal layer, and printing a dielectric spacer layer on the first dielectric layer. At least one semiconductor chip is attached to either the first or the second metal layer. A first layer assembly comprising the first metal layer, the first dielectric layer, the dielectric spacer layer and a second layer assembly comprising the second metal layer and the second dielectric layer are brought together. The first and second layer assemblies are laminated to form a laminate insert package, whereby the at least one semiconductor chip is embedded within the laminate insert package.

Abstract translation: 一种制造叠层嵌件封装的方法包括提供第一金属层，在第一金属层上印刷第一介电层，提供第二金属层，在第二金属层上印刷第二介电层，以及将介质间隔层印刷在 第一介电层。 至少一个半导体芯片附接到第一或第二金属层。 包括第一金属层，第一介电层，电介质间隔层和包括第二金属层和第二介电层的第二层组件的第一层组件被聚集在一起。 第一层和第二层组件被层压以形成层压嵌件封装，由此将至少一个半导体芯片嵌入在层叠插件封装内。

公开(公告)号：US20120302010A1

公开(公告)日：2012-11-29

申请号：US13561247

申请日：2012-07-30

Applicant: Takashi KARIYA ,  Akira Mochida

Inventor： Takashi KARIYA ,  Akira Mochida

IPC: H01L21/58

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.

Abstract translation: 一种制造印刷电路板的方法包括在第一金属层上形成含有原料陶瓷材料的未煅烧层，焙烧形成在第一金属层上的未煅烧层，使得具有以片状形式煅烧的陶瓷体的高介电常数层 形成在第一金属层上，相对于第一金属层在高介电常数层的相对侧的高介电常数层上形成第二金属层，使得具有高介电常数层的层状电容器和第一金属层 形成夹着高介电常数层的第二层电极，并将层叠电容器配置在主体中。