公开(公告)号：US20090233468A1

公开(公告)日：2009-09-17

申请号：US12285893

申请日：2008-10-16

Applicant: Shiro Yamashita ,  Hideto Yoshinari

Inventor： Shiro Yamashita ,  Hideto Yoshinari

IPC: H01R12/00

CPC classification number: H05K1/119 ,  H05K1/0366 ,  H05K1/056 ,  H05K1/141 ,  H05K3/308 ,  H05K3/42 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2201/1059 ,  H05K2201/10803 ,  Y10S439/941

Abstract: In a module, press-fit connection using a pin terminal including a connection part separated into two parts and a flat plane parallel to the lengthwise direction in the separation part and perpendicular to the separation direction of the pin terminal is performed. A through-hole of a board is structured so that an inner diameter of the through-hole at a middle part in the thickness direction of the board is smaller than that at obverse and reverse surfaces of the board and the length of the middle part of the through-hole connected to the pin terminal is shorter than the length of the flat plane of the pin terminal.

Abstract translation: 在模块中，使用包括分离成两部分的连接部分的引脚端子和在分离部分中与长度方向平行的平面并且垂直于引脚端子的分离方向的压配合连接。 板的通孔的结构使得板的厚度方向中间部分处的通孔的内径小于板的正面和反面以及中间部分的长度 连接到引脚端子的通孔比引脚端子的平面的长度短。

公开(公告)号：US20170149154A1

公开(公告)日：2017-05-25

申请号：US15423269

申请日：2017-02-02

Applicant: MERCURY SYSTEMS, INC.

Inventor： Darryl J. MCKENNEY ,  Absu METHRATTA ,  Erica OUELLETTE

IPC: H01R12/58 ,  H05K1/02 ,  H01R12/71

CPC classification number: H01R12/716 ,  H01R4/028 ,  H01R9/091 ,  H01R12/526 ,  H01R12/58 ,  H01R12/714 ,  H01R13/05 ,  H01R13/405 ,  H01R13/652 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/308 ,  H05K3/34 ,  H05K3/421 ,  H05K2201/09545 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2201/10189 ,  H05K2201/10295 ,  H05K2201/1078 ,  H05K2201/10803 ,  H05K2201/10878 ,  H05K2201/10901 ,  Y02P70/611

Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.

公开(公告)号：US09106005B2

公开(公告)日：2015-08-11

申请号：US13356791

申请日：2012-01-24

Applicant: Takeshi Okuyama ,  Toshihiro Kusagaya ,  Tohru Yamakami

Inventor： Takeshi Okuyama ,  Toshihiro Kusagaya ,  Tohru Yamakami

IPC: H01L23/48 ,  H01R12/57 ,  H01R4/02 ,  H05K3/34 ,  H01R12/72 ,  H01R13/6587 ,  H05K1/02

CPC classification number: H05K3/3426 ,  H01R4/028 ,  H01R12/57 ,  H01R12/724 ,  H01R13/6587 ,  H05K1/025 ,  H05K3/3494 ,  H05K2201/10189 ,  H05K2201/10757 ,  H05K2201/10803 ,  H05K2201/10909 ,  H05K2201/2081 ,  H05K2203/04 ,  Y02P70/613

Abstract: Disclosed is a surface mount device to be mounted on a base member, including plural lead units, each of the plural lead units including, a lead including a body portion and a foot formed at an end of the lead; a solder portion formed at the foot of the lead to protrude toward the direction of the base member to have a summit portion, and a diffusion prevention portion provided on the lead for preventing a diffusion of a solder along the body portion of the lead.

Abstract translation: 公开了一种表面安装装置，其安装在基座构件上，包括多个引线单元，所述多个引线单元中的每一个包括：引线，其包括形成在引线端部的主体部分和脚部; 形成在引脚的脚部处的焊料部分朝向基部构件的方向突出以具有顶部部分，以及设置在引线上的防止扩散部分，用于防止焊料沿引线的主体部分扩散。

公开(公告)号：US20150222265A1

公开(公告)日：2015-08-06

申请号：US14606447

申请日：2015-01-27

Applicant: Anden Co., Ltd.

Inventor： Hideyuki OHTANI ,  Naoyuki YASUDA

IPC: H03K17/693 ,  H03K17/687

CPC classification number: H03K17/693 ,  H03K17/6874 ,  H03K17/6877 ,  H05K3/3426 ,  H05K2201/10053 ,  H05K2201/10295 ,  H05K2201/10803 ,  H05K2201/1081 ,  H05K2201/10833 ,  H05K2201/10871 ,  Y02P70/613

Abstract: In a relay module device, a signal converting section transmits driving signals of switching elements when receiving input signals from an external device and sets a relationship between the input signals and the driving signals. The relationship includes a first mode in which the signal converting section transmits the driving signals to separately control one of the switching elements with respect to one of the input signals, and a second mode in which the signal converting section transmits the driving signals to concurrently control two or more of the switching elements with respect to one of the input signals.

Abstract translation: 在继电器模块装置中，当从外部装置接收输入信号时，信号转换部分传输开关元件的驱动信号，并设定输入信号与驱动信号之间的关系。 该关系包括第一模式，其中信号转换部分发送驱动信号以相对于输入信号之一单独控制开关元件之一;以及第二模式，其中信号转换部分将驱动信号传输到同时控制 相对于输入信号之一的两个或多个开关元件。

公开(公告)号：US20130133193A1

公开(公告)日：2013-05-30

申请号：US13305502

申请日：2011-11-28

Applicant: Chih-Tai Hsu ,  Nan-Cheng Chen ,  Chih-Ming Chiang ,  Hung-Chang Hung ,  Xin Zhong

Inventor： Chih-Tai Hsu ,  Nan-Cheng Chen ,  Chih-Ming Chiang ,  Hung-Chang Hung ,  Xin Zhong

IPC: H05K3/34 ,  H05K3/12

CPC classification number: H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/00015 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/1225 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/09427 ,  H05K2201/10803 ,  H05K2201/10969 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/53174 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a surface mount technology process for an advanced quad flat no-lead package process and a stencil used therewith. The surface mount technology process for an advanced quad flat no-lead package includes providing a printed circuit board. A stencil with first openings is mounted over the printed circuit board. A solder paste is printed passing the first openings to form first solder paste patterns. The stencil is taken off. A component placement process is performed to place the advanced quad flat no-lead package comprising a die pad on the printed circuit board, wherein the first solder paste patterns contact a lower surface of the die pad, and an area ratio of the first openings to the lower surface of the die pad is between 1:2 and 1:10. A reflow process is performed to melt the first solder paste patterns to surround a sidewall of the die pad.

Abstract translation: 本发明提供了一种用于高级四边形扁平无铅封装工艺的表面贴装技术工艺和与其一起使用的模板。 用于高级四边形扁平无铅封装的表面贴装技术工艺包括提供印刷电路板。 具有第一开口的模板安装在印刷电路板上。 印刷焊膏通过第一开口形成第一焊膏图案。 模具被取下。 执行部件放置处理以将包括管芯焊盘的高级四边形扁平无引线封装放置在印刷电路板上，其中第一焊膏图案接触管芯焊盘的下表面，并且将第一开口与 芯片焊盘的下表面在1:2与1:10之间。 进行回流处理以熔化第一焊膏图案以围绕管芯焊盘的侧壁。

公开(公告)号：US20080144260A1

公开(公告)日：2008-06-19

申请号：US11979972

申请日：2007-11-13

Applicant: Takayoshi Honda

Inventor： Takayoshi Honda

IPC: H05K7/00

CPC classification number: H05K1/116 ,  H01R12/707 ,  H01R43/0256 ,  H05K1/023 ,  H05K3/3405 ,  H05K3/3447 ,  H05K3/3484 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09709 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2201/10757 ,  H05K2201/10787 ,  H05K2201/10803 ,  H05K2201/10871 ,  H05K2201/10901 ,  H05K2203/1178 ,  H05K2203/1394

Abstract: An electronic device includes a printed circuit board having lands and an electronic element having a body and terminals. First and second lands provide a zigzag pattern. Each first land is coupled with the first terminal, and each second land is coupled with the second terminal. The second terminal includes a first parallel member, a first connection member, a second parallel member and a first mounting member. The first parallel member is completely embedded in the body, or another part of the first parallel member exposed from the body is shorter than the second parallel member. A second height between the second parallel member and the printed circuit board is smaller than a first height between the first parallel member and the printed circuit board.

Abstract translation: 电子设备包括具有平台的印刷电路板和具有主体和端子的电子元件。 第一和第二个土地提供锯齿形图案。 每个第一焊盘与第一端子耦合，并且每个第二焊盘与第二端子耦合。 第二端子包括第一平行构件，第一连接构件，第二平行构件和第一安装构件。 第一平行构件完全嵌入主体中，或者从主体露出的第一平行构件的另一部分比第二平行构件短。 第二平行构件和印刷电路板之间的第二高度小于第一平行构件和印刷电路板之间的第一高度。

公开(公告)号：US3362005A

公开(公告)日：1968-01-02

申请号：US64904967

申请日：1967-06-26

Applicant: BERG ELECTRONICS INC

Inventor： CORNS WILLIAM M

IPC: H01R4/02 ,  H01R12/52 ,  H01R12/59 ,  H02B1/20 ,  H02J7/14 ,  H05K1/14 ,  H05K3/30 ,  H05K3/32 ,  H05K3/36

CPC classification number: H01R12/59 ,  H01R12/52 ,  H05K1/148 ,  H05K3/308 ,  H05K3/361 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/1059 ,  H05K2201/10803

公开(公告)号：US3059152A

公开(公告)日：1962-10-16

申请号：US79225259

申请日：1959-02-05

Applicant: GLOBE UNION INC

Inventor： KHOURI ALFRED S

IPC: H01R12/00 ,  H05K3/30 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K3/308 ,  H05K3/3447 ,  H05K3/4046 ,  H05K2201/10696 ,  H05K2201/10803 ,  H05K2201/10818 ,  H05K2201/10871 ,  H05K2201/10878 ,  Y10T29/49945

公开(公告)号：US20180062290A1

公开(公告)日：2018-03-01

申请号：US15683051

申请日：2017-08-22

Applicant: Sumitomo Wiring Systems, Ltd.

Inventor： Hideki Goto

IPC: H01R12/71 ,  H01R12/70

CPC classification number: H01R12/718 ,  H01R4/02 ,  H01R12/526 ,  H01R12/585 ,  H01R12/7064 ,  H05K3/308 ,  H05K3/3447 ,  H05K2201/10295 ,  H05K2201/1059 ,  H05K2201/10787 ,  H05K2201/10803

Abstract: Provided is a substrate terminal-equipped printed circuit board having configured to enable a substrate terminal to be fixed to a printed circuit board without using a pedestal, and to reduce the pressure and the insertion force applied to an inner surface of a through hole when the substrate terminal is press-fitted therein. A conducting portion of a substrate terminal includes: a press-fitted portion disposed at a proximal end portion thereof and is press-fitted into a through hole; and a loosely inserted portion that extends from the press-fitted portion to a distal end portion thereof, has a narrower width than the press-fitted portion, and is inserted into the through hole with a gap therebetween, and the press-fitted portion of the conducting portion is in pressure contact only with printed wiring provided on a surface layer of the printed circuit board and with an insulating layer located immediately below the printed wiring.

公开(公告)号：US20170318684A1

公开(公告)日：2017-11-02

申请号：US15652337

申请日：2017-07-18

Applicant: OLYMPUS CORPORATION

Inventor： Jumpei YONEYAMA

IPC: H05K3/40 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K3/40 ,  H05K1/11 ,  H05K3/3405 ,  H05K3/368 ,  H05K3/4092 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09827 ,  H05K2201/1075 ,  H05K2201/10787 ,  H05K2201/10803 ,  H05K2201/10931

Abstract: A method of manufacturing a wiring board includes a stacking process in which N (N is an integer equal to or greater than 2) wiring layers, end portions of which include linear conductor patterns, are stacked, with the end portions superimposed, via substrates (insulating layers) provided among the wiring layers and a laminated plate is manufactured and a removing process in which the insulating layers around the end portions of the conductor patterns of the laminated plate are removed to machine the end portions into N flying leads projecting from an end face.