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    Circuit board configured to provide multiple interfaces
    193.
    发明申请
    Circuit board configured to provide multiple interfaces 失效
    电路板配置为提供多个接口

    公开(公告)号：US20030122575A1

    公开(公告)日：2003-07-03

    申请号：US10330821

    申请日：2002-12-27

    Inventor： Ji Eun Jang ,  Jae Jin Lee

    IPC: H03K019/003

    CPC classification number: H05K1/0246 ,  G11C7/10 ,  G11C11/4093 ,  H03K19/0175 ,  H05K1/0286 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022

    Abstract: A circuit board configured to provide multiple interfaces is disclosed. The circuit board comprises a termination slot inserted with a termination module configured to modulate circuits by applying a termination resistance and a termination voltage. If the termination module is inserted into the termination slot, the circuit board operates as a series stub terminated transceiver logic (SSTL) interface. Otherwise, the board operates as a low voltage transistor logic (LVTTL) interface. Additionally, the board comprises a switch configured to selectively connect a termination resistance to a bus. If the switch connects the termination resistance to the bus, the board operates as an SSTL interface. Otherwise, the board operates as an LVTTL interface.

    Abstract translation: 公开了一种被配置为提供多个接口的电路板。 电路板包括插入有终端模块的终端插槽，其配置成通过施加终端电阻和终止电压来调制电路。 如果终端模块插入终端插槽，则电路板作为串行存根终端收发器逻辑（SSTL）接口运行。 否则，该板作为低电压晶体管逻辑（LVTTL）接口工作。 另外，电路板包括被配置为选择性地将终端电阻连接到总线的开关。 如果开关将终端电阻连接到总线，则该板作为SSTL接口工作。 否则，该板作为LVTTL接口运行。

    High speed, controlled impedance air dielectric circuit modules for electronic backplane systems
    194.
    发明申请
    High speed, controlled impedance air dielectric circuit modules for electronic backplane systems 审中-公开
    用于电子背板系统的高速，可控阻抗空气介质电路模块

    公开(公告)号：US20030112091A1

    公开(公告)日：2003-06-19

    申请号：US10273410

    申请日：2002-10-17

    Inventor： Timothy A. Lemke ,  Richard A. Elco

    IPC: H01P005/02

    CPC classification number: H05K1/024 ,  H01P3/08 ,  H05K1/14 ,  H05K3/10 ,  H05K3/202 ,  H05K2201/044 ,  H05K2201/09318

    Abstract: A novel backplane interconnection system that is useful in the telecommunication and data process industries for ultra high speed backplane systems. It is capable of transmitting digital signals with bandwidths of 10 GHz and beyond. The invention provides high performance at a low cost of manufacture. It is suitable for use in a wide variety of system applications. One embodiment of the invention comprises an air dielectric and copper conductor matched impedance transmission line system that interconnects daughter cards in a conventional backplane configuration. The high speed transmission-line structure is continuous through the backplane-daughter card and return path. Such embodiment are also integrated with conventional printed circuit backplanes or be a stand-alone device.

    Abstract translation: 一种新颖的背板互连系统，适用于超高速背板系统的电信和数据处理行业。 它能够传输10 GHz及以上带宽的数字信号。 本发明以低成本制造提供高性能。 适用于各种系统应用。 本发明的一个实施例包括在传统背板配置中互连子卡的空气电介质和铜导体匹配阻抗传输线系统。 高速传输线结构通过背板 - 子卡和返回路径是连续的。 这种实施例也与常规印刷电路底板集成或者是独立设备。

    Motherboard memory slot ribbon cable and methods, apparatus and systems employing same
    195.
    发明申请
    Motherboard memory slot ribbon cable and methods, apparatus and systems employing same 失效
    主板内存插槽带状电缆及其使用方法，设备和系统

    公开(公告)号：US20030016040A1

    公开(公告)日：2003-01-23

    申请号：US09908511

    申请日：2001-07-18

    Inventor： Steven J. Brunelle ,  Saeed Momenpour

    IPC: G01R031/02

    CPC classification number: H05K7/1431 ,  G11C5/04 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H05K1/14 ,  H05K1/147 ,  H05K3/222 ,  H05K2201/044 ,  H05K2201/10159 ,  H05K2201/10325 ,  H05K2203/162

    Abstract: A testing apparatus, system and method for testing computer memory modules. The apparatus includes a motherboard having a processor and at least one resident memory socket fixed to the motherboard. A remote-memory socket is provided and located a distance from the resident memory socket, such as on a periphery of the motherboard. The remote memory socket is coupled to the resident memory socket by a conductor assembly such as a ribbon cable and an adapter. A memory module is placed in the remote memory socket and tested using a signal or combination of signals from the processor. A plurality of motherboards, each being configured with remote memory sockets, may be combined to form a testing system suitable for use with an automated handler.

    Abstract translation: 一种用于测试计算机内存模块的测试设备，系统和方法。 该装置包括具有处理器的主板和固定到主板的至少一个驻留存储器插槽。 提供远程存储器插座，并且位于与驻留的存储器插座（例如在主板的外围）上一定距离处。 远程存储器插座通过诸如带状电缆和适配器的导体组件耦合到驻留的存储器插槽。 存储器模块放置在远程存储器插槽中，并使用来自处理器的信号或信号的组合进行测试。 每个配置有远程存储器插槽的多个主板可以组合以形成适合于与自动处理程序一起使用的测试系统。

    Memory address driver circuit
    196.
    发明授权
    Memory address driver circuit 有权
    内存地址驱动电路

    公开(公告)号：US06370053B2

    公开(公告)日：2002-04-09

    申请号：US09761880

    申请日：2001-01-17

    Applicant: Nai-Shung Chang ,  Chia-Hsin Chen

    Inventor： Nai-Shung Chang ,  Chia-Hsin Chen

    IPC: G11C502

    CPC classification number: H05K1/0246 ,  G11C8/06 ,  G11C8/12 ,  H05K1/0262 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022 ,  H05K2201/10159

    Abstract: A memory address driver circuit with memory module slots on a computer main board that can be divided into two groups. One group of memory module slots includes the slots whose trace line to a control chipset is smaller than 2500 mils or closest to the control chipset. The other group of memory module slots includes all the remaining slots. The control chipset includes two memory control circuits. The memory control circuit for supporting DDR DRAM is connected to the address leads of the memory module slot closest to the control chipset. However, no terminal resistors are connected to any address leads of the memory module slot. Hence, engineers may have to design one set of terminal resistors only. In addition, the memory control circuit uses one-cycle access command timing to boost system performance.

    Abstract translation: 一个内存地址驱动电路，其内存模块插槽位于计算机主板上，可分为两组。 一组存储器模块插槽包括其控制芯片组的跟踪线小于2500密耳或最接近控制芯片组的插槽。 另一组内存模块插槽包括所有剩余的插槽。 控制芯片组包括两个存储器控制电路。 用于支持DDR DRAM的存储器控​​制电路连接到最靠近控制芯片组的存储器模块插槽的地址引线。 但是，没有端子电阻连接到内存模块插槽的任何地址引线。 因此，工程师可能只需要设计一组端子电阻。 此外，存储器控制电路使用一周期访问命令定时来提高系统性能。

    Motherboard with board having terminating resistance
    197.
    发明授权
    Motherboard with board having terminating resistance 失效
    具有终端电阻的主板

    公开(公告)号：US06328572B1

    公开(公告)日：2001-12-11

    申请号：US09626357

    申请日：2000-07-27

    Applicant: Hiroshi Higashida ,  Kimiyasu Makino

    Inventor： Hiroshi Higashida ,  Kimiyasu Makino

    IPC: H01R1200

    CPC classification number: H05K7/1458 ,  G06F13/409 ,  H05K1/023 ,  H05K1/141 ,  H05K3/366 ,  H05K3/368 ,  H05K2201/044 ,  H05K2201/10022 ,  H05K2201/10189

    Abstract: The motherboard MB1 of the present invention is a motherboard comprising a plurality of plug connectors 12 installed on the front face of the board 11 and a bus line for inter-connecting these plug connectors so as to allow inter-communication of daughter boards DB1-DB7 connected to the plug connectors 12. The motherboard is configured such that a termination board TB1 having a terminating resistance to decrease reflection noise of the bus line is connected to the plug connector at the last slot S8 of the bus line among the plug connectors 12, 12, . . . installed on the front face of the motherboard. Alternatively, the motherboard is configured such that the termination board is connected to the rear face of the last slot S8.

    Abstract translation: 本发明的母板MB1是包括安装在板11的前面上的多个插头连接器12和用于将这些插头连接器相互连接的母线的母板，以允许子板DB1-DB7的相互连通 连接到插头连接器12.主板被配置为使得具有端接电阻以减少总线线路的反射噪声的终端板TB1在插头连接器12之间的总线的最后时隙S8处连接到插头连接器， 12，。 。 。 安装在主板的正面。 或者，主板被配置为使得终端板连接到最后一个槽S8的后表面。

    High-frequency bus system
    198.
    发明授权
    High-frequency bus system 失效
    高频总线系统

    公开(公告)号：US06266730B1

    公开(公告)日：2001-07-24

    申请号：US09507303

    申请日：2000-02-18

    Applicant: Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

    Inventor： Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

    IPC: H05K102

    CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

    Abstract: A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.

    Abstract translation: 尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。 高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。 第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。 高频总线系统还包括没有与其连接的设备的第二总线段。 第二总线段还具有用于传播高频信号的至少一对传输线。 第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个 设备在大致相同的时间连接到第一总线段。 而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。 尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间 或控制，由信号携带。

    Signaling improvement using extended transmission lines on high speed DIMMS
    199.
    发明授权
    Signaling improvement using extended transmission lines on high speed DIMMS 失效
    在高速DIMMS上使用扩展传输线进行信号改进

    公开(公告)号：US6142830A

    公开(公告)日：2000-11-07

    申请号：US36319

    申请日：1998-03-06

    Applicant: Steffen Loeffler

    Inventor： Steffen Loeffler

    IPC: H01L25/00 ,  G06F12/00 ,  G06F13/16 ,  G11C5/00 ,  G11C5/06 ,  G11C11/401 ,  H01L27/10 ,  H05K1/02 ,  H05K1/14 ,  H01R13/66

    CPC classification number: H05K1/14 ,  G11C5/04 ,  G11C5/063 ,  H05K1/0246 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2203/1572

    Abstract: A circuit board such as a memory module board mounts a plurality of memory modules that are electrically connected to a module bus on a first surface of the board. The module bus is coupled to a connector at a first end thereof that permits an electrical coupling of a plurality of electrical conductors of the module bus to an external large integrated circuit board, and a terminating resistor device at a second end thereof for properly terminating predetermined ones of the plurality of electrical conductors of the module bus. The module bus is extended beyond the last memory module along the bus by a length which is sufficient to substantially limit reflections and/or crosstalk between the conductors and thereby improve signaling along the module bus. In a first embodiment, the module bus is extended around an edge of the board and for a predetermined distance over any unused portions of the backside of the board. In a second embodiment, the module bus is extended for a maximum predetermined distance along any unused portions of the front side of the board when the backside of the board is unavailable for extending the module bus.

    Abstract translation: 诸如存储器模块板的电路板在电路板的第一表面上安装电连接到模块总线的多个存储器模块。 模块总线在其第一端处耦合到连接器，其允许模块总线的多个电导体与外部大型集成电路板的电耦合，以及在其第二端处的端接电阻器件，用于适当地终止预定的 模块总线的多个电导体中的一个。 模块总线沿着总线延伸超过最后一个存储器模块一段长度，该长度足以基本上限制导体之间的反射和/或串扰，从而改善沿着模块总线的信令。 在第一实施例中，模块总线围绕板的边缘延伸并且在板的背面的任何未使用部分上延伸预定距离。 在第二实施例中，当板的背面不可用于扩展模块总线时，模块总线沿板的正面的任何未使用部分延伸最大预定距离。

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