公开(公告)号：US07476800B2

公开(公告)日：2009-01-13

申请号：US11420954

申请日：2006-05-30

Applicant: Peter Berghofer ,  Josef Sugetich ,  Mathias Pedevilla

Inventor： Peter Berghofer ,  Josef Sugetich ,  Mathias Pedevilla

IPC: H01B7/00

CPC classification number: H01R13/03 ,  H01L31/0508 ,  H01L31/0512 ,  H01R4/188 ,  H05K3/321 ,  H05K2201/0373 ,  Y02E10/50 ,  Y10T29/4913

Abstract: An electric connection element includes an electric conductor having a surface configured, at least in regions thereof, with a structuring and/or rough surface, and an electrically conductive coating.

Abstract translation: 电连接元件包括具有至少在其区域中构造有结构和/或粗糙表面的表面的电导体和导电涂层。

公开(公告)号：US07474541B2

公开(公告)日：2009-01-06

申请号：US11383185

申请日：2006-05-12

Applicant: Tse-Hsine Laio ,  Ting-Kuo Kao

Inventor： Tse-Hsine Laio ,  Ting-Kuo Kao

IPC: H05K7/12

CPC classification number: H05K1/0209 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/0373 ,  H05K2201/09681 ,  H05K2201/09781 ,  H05K2203/043

Abstract: In a printed circuit board and its heat dissipating metal surface layout, a layer of copper foil is coated onto the printed circuit board for dissipating heat, and the surface of the copper foil is covered by an insulating coating, and a bare copper is formed on the surface of copper foil which is not covered by the insulating coating, and the bare copper is arranged in a cross shape, or in the shape of “#”, so that when the printed circuit board goes through a soldering furnace, the cohesion of solder is even instead of aggregating at a same position or the center, so as to obtain a larger protruding area and facilitate dissipating heat and transmitting current.

Abstract translation: 在印刷电路板及其散热金属表面布置中，将一层铜箔涂覆在印刷电路板上用于散热，铜箔的表面被绝缘涂层覆盖，并且裸铜形成在 未被绝缘涂层覆盖的铜箔的表面和裸铜布置成十字形或“＃”形，使得当印刷电路板通过焊接炉时，其内聚力 焊料是均匀的，而不是在相同的位置或中心处聚集，以便获得更大的突出面积并且有助于散热和传输电流。

公开(公告)号：US20080303134A1

公开(公告)日：2008-12-11

申请号：US12156875

申请日：2008-06-05

Applicant: Chun-Yuan Li ,  Hsiao-Jen Hung ,  Chin-Huang Chang ,  Jeng-Yuan Lai

Inventor： Chun-Yuan Li ,  Hsiao-Jen Hung ,  Chin-Huang Chang ,  Jeng-Yuan Lai

IPC: H01L23/52 ,  H01L21/02

CPC classification number: H01L21/4832 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/27 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H05K3/341 ,  H05K3/3436 ,  H05K2201/0373 ,  H05K2201/09472 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a method for fabricating the same are disclosed, which includes: providing a carrier board, forming a plurality of metal bumps on the carrier board, forming a metal layer on the carrier board to encapsulate the metal bumps, having at least one semiconductor chip electrically connected to the metal layer, then forming an encapsulant on the carrier board to encapsulate the semiconductor chip, and next removing the carrier board and the metal bumps to correspondingly form a plurality of grooves on surface of the encapsulant, wherein bottom and sides of the grooves are covered with the metal layer to allow electroconductive components to be effectively positioned in the grooves and completely bonded with the metal layer.

Abstract translation: 公开了一种半导体封装及其制造方法，其包括：提供载体板，在载体板上形成多个金属凸块，在载体板上形成金属层以封装金属凸块，具有至少一个 半导体芯片与金属层电连接，然后在载体板上形成密封剂以封装半导体芯片，接着去除载体板和金属凸块，以在密封剂的表面上相应地形成多个凹槽，其中底部和侧面 的沟槽被金属层覆盖以允许导电部件有效地定位在槽中并与金属层完全粘合。

公开(公告)号：US20080283284A1

公开(公告)日：2008-11-20

申请号：US12120864

申请日：2008-05-15

Applicant: Masayoshi KOYAMA ,  Tsukasa SHIRAISHI

Inventor： Masayoshi KOYAMA ,  Tsukasa SHIRAISHI

IPC: H01R12/04

CPC classification number: H05K3/361 ,  H01L24/11 ,  H01L2924/00014 ,  H05K1/117 ,  H05K3/323 ,  H05K2201/0373 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09745 ,  H05K2203/087 ,  H05K2203/166 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2224/05599

Abstract: A wiring board connection method connects wiring boards each having a strip-shaped connection terminal for connecting with another substrate, the method including the steps of: aligning the wiring boards so that the connection terminals face each other with a fluid interposed therebetween; and bonding the connection terminals with each other by heating and then-cooling the fluid, wherein: the fluid is a material that generates air bubbles upon being heated; a plurality of the connection terminals are provided on each of the wiring boards; and a groove is formed in each of at least one of the connection terminals in at least one of the wiring boards, the groove extending across the relevant connection terminal.

Abstract translation: 接线板连接方法连接各自具有用于与另一基板连接的条形连接端子的布线板，该方法包括以下步骤：使布线板对准，使得连接端子彼此间插入流体; 以及通过加热然后冷却所述流体而将所述连接端子彼此接合，其中：所述流体是在被加热时产生气泡的材料; 多个连接端子设置在每个布线板上; 并且在至少一个所述布线板中的至少一个所述连接端子中的每一个中形成凹槽，所述凹槽延伸穿过所述相关连接端子。

公开(公告)号：US07454147B2

公开(公告)日：2008-11-18

申请号：US11703782

申请日：2007-02-08

Applicant: Seung-deog An ,  Min-seon Kim

Inventor： Seung-deog An ,  Min-seon Kim

IPC: G03G15/00

CPC classification number: H05K1/11 ,  H05K3/325 ,  H05K2201/0373 ,  H05K2201/09663 ,  H05K2201/09781 ,  H05K2201/10265 ,  H05K2203/044

Abstract: Disclosed is a printed circuit board comprising a contact terminal, which prevents a poor contact and reduces a manufacturing cost, and an image forming apparatus having the same. The printed circuit board comprises a circuit part for controlling and processing an operation of electronic appliance, and a large-area contact terminal formed by a group of small-area terminals for electric connection with external device. The small-area terminals can be formed in various types, respectively having regular size and shape and being distanced a predetermined interval. Accordingly, unevenness of the large-area contact terminal surface caused by soldering is prevented since a plurality of small-area terminals constitute a unit contact terminal of over a predetermined size. Therefore, quality of contact with external terminal improves. Further, manufacturing cost is reduced, and the manufacturing process becomes simple.

Abstract translation: 公开了一种印刷电路板，其包括接触端子，其防止接触不良并降低制造成本，以及具有该接触端子的图像形成装置。 印刷电路板包括用于控制和处理电子设备的操作的电路部分和由一组用于与外部设备电连接的小区域端子形成的大面积接触端子。 小区域终端可以形成为各种类型，分别具有规则的大小和形状，并且以预定的间隔间隔开。 因此，由于多个小区域端子构成超过预定尺寸的单元接触端子，因此防止了由焊接引起的大面积接触端子表面的不均匀性。 因此，与外部端子的接触质量提高。 此外，制造成本降低，制造过程变得简单。

公开(公告)号：US20080253090A1

公开(公告)日：2008-10-16

申请号：US12089668

申请日：2006-08-25

Applicant: Christian Janisch ,  Karl Smirra

Inventor： Christian Janisch ,  Karl Smirra

IPC: H05K7/20

CPC classification number: H01L23/3677 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K3/0061 ,  H05K2201/0373 ,  H05K2201/09054 ,  H05K2201/10689 ,  H01L2924/00

Abstract: An IC component has a cooling arrangement that is embodied as an electronic housing provided with a cooling body. The IC component is directly disposed on the cooling body in the electronic housing. The invention advantageously provides a cooling arrangement for IC components that enables the IC component to be efficiently and directly cooled and assembled in a simple manner, without requiring additional components. It is especially suitable for applications in electronic housings in the automotive field.

Abstract translation: IC部件具有作为设置有冷却体的电子壳体的冷却装置。 IC部件直接设置在电子壳体的冷却体上。 本发明有利地提供了用于IC部件的冷却装置，其能够以简单的方式有效且直接地冷却和组装IC部件，而不需要额外的部件。 它特别适用于汽车领域的电子外壳应用。

公开(公告)号：US07348494B1

公开(公告)日：2008-03-25

申请号：US09821722

申请日：2001-03-29

Applicant: Martin R. Handforth ,  Herman Kwong ,  Richard R. Goulette

Inventor： Martin R. Handforth ,  Herman Kwong ,  Richard R. Goulette

IPC: H05K1/16

CPC classification number: H05K3/368 ,  H01R12/52 ,  H01R12/61 ,  H05K1/0218 ,  H05K1/117 ,  H05K3/365 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/0715 ,  H05K2201/0919 ,  H05K2201/10598

Abstract: Inner layer traces on a multilayer printed wiring board are exposed to enable direct interconnection with another device such as a printed wiring board. The traces may be exposed by removing at least some of the dielectric substrate material around the traces, or by extending the traces beyond the other layers of the printed wiring board. Corresponding conductors associated with the other device are placed in direct physical contact with the exposed inner layer traces, and may be aligned and secured with guide plates, alignment pins and spring members. Such direct connection mitigates the need for vias, and has more favorable electrical characteristics for high frequency signal transmission.

Abstract translation: 暴露多层印刷线路板上的内层迹线，以便能够与诸如印刷电路板的其它器件直接互连。 可以通过去除迹线周围的至少一些电介质基板材料，或者通过将迹线延伸超过印刷线路板的其它层来暴露迹线。 与另一装置相关联的相应的导体被放置成与暴露的内层迹线直接物理接触，并且可以与引导板，对准销和弹簧构件对准和固定。 这种直接连接减轻了对通孔的需要，并且对于高频信号传输具有更有利的电特性。

公开(公告)号：US07317322B2

公开(公告)日：2008-01-08

申请号：US11243702

申请日：2005-10-05

Applicant: Warren M. Farnworth ,  Salman Akram

Inventor： Warren M. Farnworth ,  Salman Akram

IPC: G01R31/02

CPC classification number: H05K3/326 ,  G01R1/0466 ,  G01R31/2853 ,  H05K1/118 ,  H05K3/4092 ,  H05K2201/0373 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09081 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/4914 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.

Abstract translation: 用于测试半导体部件的互连件包括基板和基板上的触点，用于与部件上的凸起触点进行临时电连接。 每个接触件包括一个凹部和悬在该凹部上的引线图案，其构造成电接合凸起的触点。 引线适于在凹部内在z方向上移动以适应凸起接触件的高度和平面度的变化。 此外，引线可以包括用于穿透凸起的触点的突起，用于防止与凸起的触点接合的非结合外层以及与凸起的触点的形状相匹配的弯曲形状。 可以通过在基板上形成图案化的金属层，通过将聚合物基板与其上的引线附接到基板上，或者蚀刻基板以形成导电梁来形成引线。

公开(公告)号：US07302757B2

公开(公告)日：2007-12-04

申请号：US11204699

申请日：2005-08-16

Applicant: Jeffrey A. Brody ,  Hsichang Liu ,  Hai Pham Longworth ,  James C. Monaco ,  Gerard J. Nuzback ,  Wei Zou

Inventor： Jeffrey A. Brody ,  Hsichang Liu ,  Hai Pham Longworth ,  James C. Monaco ,  Gerard J. Nuzback ,  Wei Zou

IPC: H01K3/10

CPC classification number: H05K3/325 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10348 ,  H05K2201/10719 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An improved Land Grid Array interconnect structure is provided with the use of small metal bumps on the substrate electrical contact pad. The bumps interlock with segments of the fuzz button connection and increase the physical contact surface area between the contact pad and fuss button. The improved contact reduces displacement of electrical contact points due to thermo-mechanical stress and lowers the required actuation force during assembly.

Abstract translation: 提供了一种改进的Land Grid阵列互连结构，其中在基板电接触焊盘上使用小的金属凸块。 凸起与绒头按钮连接的部分互锁，并增加接触垫和大按钮之间的物理接触表面积。 改进的接触减少了由于热机械应力引起的电接触点的位移，并降低了组装过程中所需的致动力。

公开(公告)号：US20070273017A1

公开(公告)日：2007-11-29

申请号：US11439016

申请日：2006-05-23

Applicant: John J. Maloney ,  Robert M. Smith ,  Charles H. Wilson

Inventor： John J. Maloney ,  Robert M. Smith ,  Charles H. Wilson

IPC: H01L23/48

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15747 ,  H01L2924/181 ,  H05K3/341 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10689 ,  H05K2201/10727 ,  H05K2201/10969 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved.

Abstract translation: QFN封装，具有改进的焊点厚度，可提高二级附着疲劳寿命。 QFN芯片载体的铜引线框架在第二级附接之前在芯片连接焊盘区域和周围的引线区域中设置有圆形突起。 圆形的突出突起由引线框架的铜的铜本身形成。 这可以通过在电镀之前将凹坑冲压到引线框架的铜板的一个表面中以在相对表面上形成突起来实现。 形成圆形突起的这种方法简化了形成支座的过程。 突起提供了增加润湿面积的结构，并且允许使用更大量的焊料以增加焊接接​​头厚度和更好的焊盘焊接区域覆盖。 由于焊接接头厚度的增加，二级疲劳寿命显着提高。 由于焊盘焊接区域覆盖率的提高，芯片载体的热性能也得到了显着提高。