公开(公告)号：US20110233262A1

公开(公告)日：2011-09-29

申请号：US13156736

申请日：2011-06-09

Applicant: Stephen L. Buchwalter ,  Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

Inventor： Stephen L. Buchwalter ,  Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

IPC: B23K3/06 ,  B23P11/00

CPC classification number: B23K3/0638 ,  B23K3/08 ,  B23K2101/42 ,  H01L21/4853 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K1/111 ,  H05K3/3457 ,  H05K2201/09472 ,  H05K2203/0126 ,  Y10T29/49826 ,  Y10T156/1062 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A portion of compliant material includes four walls defining a slot. The slot has a relatively large cross-section end in fluid communication with a solder reservoir, and also has a relatively small cross-section end opposed to the relatively large cross-section end. The slot has a generally elongate rectangular shape when viewed in plan, with a length perpendicular to a scan direction, a width, parallel to the scan direction, associated with the relatively large cross section end, and a width, parallel to the scan direction, associated with the relatively small cross section end. The slot is configured in the portion of compliant material such that the relatively small cross-section end of the slot normally remains substantially closed, but locally opens sufficiently to dispense solder from the reservoir when under fluid pressure and locally unsupported by a workpiece. Methods of operation and fabrication are also disclosed.

Abstract translation: 柔性材料的一部分包括限定槽的四个壁。 狭槽具有与焊料储存器流体连通的相对较大的横截面端，并且还具有与相对大的横截面端相对的相对较小的横截面端。 当在平面中观察时，狭槽具有大致细长的矩形形状，其垂直于扫描方向的长度，与扫描方向平行的宽度，与相对大的横截面端相关联，并且平行于扫描方向的宽度， 与相对较小的截面端相关联。 狭槽配置在柔性材料的部分中，使得狭槽的相对小的横截面端部通常保持基本上闭合，但是当处于流体压力下并且局部地不被工件支撑时，局部开口足够地从储存器分配焊料。 还公开了操作和制造方法。

公开(公告)号：US08022553B2

公开(公告)日：2011-09-20

申请号：US12155555

申请日：2008-06-05

Applicant: Jin-Yong Ahn ,  Chang-Sup Ryu ,  Byung-Youl Min ,  Myung-Sam Kang

Inventor： Jin-Yong Ahn ,  Chang-Sup Ryu ,  Byung-Youl Min ,  Myung-Sam Kang

IPC: H01L23/48

CPC classification number: H05K1/113 ,  H01L23/13 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/20 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09472 ,  H01L2224/0401

Abstract: A mounting substrate and a method of manufacturing the mounting substrate. The mounting substrate can include an insulation layer, a bonding pad buried in one side of the insulation layer in correspondence with a mounting position of a chip, and a circuit pattern electrically connected to the bonding pad. By utilizing certain embodiments of the invention, the process for stacking a solder resist layer can be omitted, as the bonding pads can be implemented in a form recessed from the surface of the insulation layer. In this way, the manufacturing process can be simplified and manufacturing costs can be reduced. Since the surface of the mounting-substrate on which to mount a chip can be kept flat without any protuberances, the occurrence of voids in the underfill can be minimized. This is correlated to obtaining a high degree of reliability, and leads to a greater likelihood of successful mounting.

Abstract translation: 一种安装基板及其制造方法。 安装基板可以包括绝缘层，与绝缘层的一侧相对应于芯片的安装位置的接合焊盘以及电连接到焊盘的电路图案。 通过利用本发明的某些实施例，可以省略堆叠阻焊层的工艺，因为焊盘可以以从绝缘层的表面凹陷的形式来实施。 以这种方式，可以简化制造过程，并且可以降低制造成本。 由于安装芯片的安装基板的表面可以保持平坦而没有任何突起，所以可以使底部填充物中的空隙的发生最小化。 这与获得高可靠性相关，并且导致成功安装的可能性更大。

公开(公告)号：US20110204911A1

公开(公告)日：2011-08-25

申请号：US12712734

申请日：2010-02-25

Applicant: Gunsei KIMOTO

Inventor： Gunsei KIMOTO

IPC: G01R31/02

CPC classification number: G01R31/2886 ,  G01R1/06727 ,  H05K1/0268 ,  H05K1/11 ,  H05K1/144 ,  H05K3/46 ,  H05K2201/041 ,  H05K2201/09472 ,  H05K2201/096 ,  H05K2201/09709

Abstract: To facilitate connection between a narrow-pitched probe assembly and a coarse-pitched printed circuit board. A prober unit in which probes are brought into contact with to-be-tested semiconductor chips to establish electrical connection between the semiconductor chips and a test unit via the probes, in which: a probe assembly and a plurality of wiring boards are prepared, the probe assembly including output terminals to be connected directly to the probes, the probe assembly being constituted by integrated regularly-arranged multiple probe groups including the output terminals, and each of the wiring boards including wiring adhering to a surface of a non-conductive film; and an n-th row of an output terminal group of the probe assembly is brought into contact with a land group provided at an end of an n-th wiring board, and a wiring terminal provided at the other end of the n-th wiring board is connected to one of a wiring board of the test unit and a connector to establish electrical connection between the to-be-tested semiconductor chips and the test unit.

Abstract translation: 为了便于窄间距探针组件和粗调印刷电路板之间的连接。 探针单元，其中探针与待测试的半导体芯片接触，以通过探针在半导体芯片和测试单元之间建立电连接，其中：准备探针组件和多个布线板， 探针组件，其包括要直接连接到探针的输出端子，探针组件由包括输出端的集成的规则排列的多个探针组构成，并且每个布线板包括附着在非导电膜表面上的布线; 并且探针组件的输出端子组的第n行与设置在第n布线板的端部的平台组接触，并且设置在第n布线的另一端的布线端子 板连接到测试单元的布线板之一和连接器，以在待测半导体芯片和测试单元之间建立电连接。

公开(公告)号：US07971973B2

公开(公告)日：2011-07-05

申请号：US11520582

申请日：2006-09-14

Applicant: Yasuhiko Maeda

Inventor： Yasuhiko Maeda

IPC: B41J2/05

CPC classification number: H05K3/361 ,  B41J2/14233 ,  B41J2002/14258 ,  B41J2002/14491 ,  H05K3/321 ,  H05K3/4611 ,  H05K2201/0367 ,  H05K2201/09472

Abstract: The electrical connection structure includes: a first substrate which has a first electrode part; a second substrate which has a second electrode part opposing the first electrode part, and a wiring pattern connected to the second electrode part; an insulating cavity substrate which is disposed between the first substrate and the second substrate and has a through hole in a position corresponding to the first electrode part, the through hole being deeper that a sum of a height of the first electrode part and a height of the second electrode part and having an opening surface area not smaller that an area of the first electrode part; and conductive material which is filled in the through hole.

Abstract translation: 电连接结构包括：具有第一电极部分的第一基板; 具有与所述第一电极部相对的第二电极部的第二基板和与所述第二电极部连接的布线图案。 绝缘腔基板，设置在所述第一基板和所述第二基板之间，并且在与所述第一电极部对应的位置具有通孔，所述通孔比所述第一电极部的高度和所述第一电极部的高度 所述第二电极部分具有不小于所述第一电极部分的面积的开口表面积; 以及填充在通孔中的导电材料。

公开(公告)号：US07918018B2

公开(公告)日：2011-04-05

申请号：US11811749

申请日：2007-06-12

Applicant: Donald C. Abbott ,  Usman M. Chaudhry

Inventor： Donald C. Abbott ,  Usman M. Chaudhry

IPC: H05K3/34

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/4985 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/27013 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0393 ,  H05K3/205 ,  H05K3/427 ,  H05K2201/09472 ,  H05K2203/0726 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a method and apparatus for fabricating a semiconductor device having a flexible tape substrate, a hole is punched in the flexible tape substrate. The flexible tape substrate includes a metal layer attached to a polyimide layer without an adhesive there between. A cover is placed on the metal layer to cap a base of the hole. A metal is deposited on the cover exposed at the base of the hole, the metal being used to form a bond with the metal layer. The metal being deposited causes the hole to be plugged up to a selective height. Upon removal of the cover, the metal may also be deposited on the metal layer to increase a thickness of the metal layer.

Abstract translation: 在制造具有柔性带基片的半导体器件的方法和装置中，在柔性带基片上冲孔。 柔性带基材包括附着在聚酰亚胺层上的金属层，其间没有粘合剂。 在金属层上放置盖以盖住孔的基部。 金属沉积在暴露在孔底部的盖上，金属用于与金属层形成结合。 沉积的金属使得孔被堵塞到选择高度。 在去除盖子时，金属也可以沉积在金属层上以增加金属层的厚度。

公开(公告)号：US20110021016A1

公开(公告)日：2011-01-27

申请号：US12923590

申请日：2010-09-29

Applicant: Yuji Awano ,  Masataka Mizukoshi

Inventor： Yuji Awano ,  Masataka Mizukoshi

IPC: H01L21/60

CPC classification number: H05K3/325 ,  B82Y10/00 ,  H01L24/12 ,  H01L24/16 ,  H01L24/90 ,  H01L2224/1134 ,  H01L2224/13193 ,  H01L2224/13582 ,  H01L2224/13693 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81899 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K2201/026 ,  H05K2201/09472 ,  H05K2201/209 ,  H01L2224/13099 ,  H01L2224/0401

Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.

Abstract translation: 公开了一种包括半导体器件的半导体封装; 电路板; 以及连接机构，其包括设置在所述半导体器件上的第一导电端子和设置在所述电路板侧的第二导电端子，所述连接机构经由所述第一导电端子和所述第二导电端子电连接所述半导体器件和所述电路板。 连接机构的第一导电端子和第二导电端子中的至少一个包括一个或多个碳纳米管，每个碳纳米管的一端固定到第一导电端子和第二导电端子中的至少一个的表面，并且延伸 在远离表面的方向上。 第一导电端子和第二导电端子通过碳纳米管彼此接合。

公开(公告)号：US20100276797A1

公开(公告)日：2010-11-04

申请号：US12433429

申请日：2009-04-30

Applicant: Stefan Landau ,  Ralf Otremba ,  Uwe Kirchner ,  Andreas Schloegl ,  Christian Fachmann ,  Joachim Mahler

Inventor： Stefan Landau ,  Ralf Otremba ,  Uwe Kirchner ,  Andreas Schloegl ,  Christian Fachmann ,  Joachim Mahler

IPC: H01L23/495 ,  H01L21/60 ,  H01L23/367

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L24/32 ,  H01L24/40 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K3/32 ,  H05K3/3442 ,  H05K3/3447 ,  H05K3/3468 ,  H05K3/3473 ,  H05K2201/09472 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K2201/10727 ,  H05K2201/10962 ,  H05K2201/10984 ,  H05K2203/0455 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a substrate having a chip island, a chip attached to the chip island, and encapsulation material deposited on the chip and part of the chip island. The chip island includes a first main face to which the chip is attached opposite a second main face, with the second main face of the chip island defining at least one cavity.

Abstract translation: 半导体器件包括具有芯片岛的衬底，附接到芯片岛的芯片以及沉积在芯片岛和芯片岛的一部分上的封装材料。 芯片岛包括第一主面，芯片与第二主面相对，芯片岛的第二主面限定至少一个空腔。

公开(公告)号：US20100189892A1

公开(公告)日：2010-07-29

申请号：US12095630

申请日：2006-12-04

Applicant: Erik Christian Nicolaas Puik ,  Edwin Johannes Theodorus Smulders

Inventor： Erik Christian Nicolaas Puik ,  Edwin Johannes Theodorus Smulders

IPC: B05D3/00 ,  B05C19/00

CPC classification number: H05K3/321 ,  B81C99/002 ,  B81C2203/032 ,  H01L21/6835 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2924/15312 ,  H05K3/28 ,  H05K2201/09472 ,  H05K2201/10704 ,  H05K2203/0178 ,  H05K2203/1105 ,  H05K2203/1121 ,  H05K2203/1446

Abstract: Method and system for moving a frozen adhesive particle towards a target body, comprising launching means (13) which are arranged to launch the particle (2) in its frozen form towards the target body (3, 4) via a movement path (14) through a gap (15) between the launching means and the target body. The medium in the gap may have a temperature above the adhesive particle's melting temperature. The launching means may be arranged to launch the particle at a high speed. The launching means and the target body may have a geometry causing that the movement path is substantially vertical or substantially horizontal.

Abstract translation: 用于将冷冻粘合剂颗粒朝向目标体移动的方法和系统，包括发射装置（13），其布置成经由移动路径（14）将颗粒（2）以冷冻形式朝向目标体（3,4）发射， 通过发射装置和目标体之间的间隙（15）。 间隙中的介质可能具有高于粘合剂颗粒的熔融温度的温度。 发射装置可以被布置成以高速度发射颗粒。 发射装置和目标体可以具有导致运动路径基本上垂直或基本水平的几何形状。

公开(公告)号：US20100151704A1

公开(公告)日：2010-06-17

申请号：US12693097

申请日：2010-01-25

Applicant: Gary Yasumura ,  Joseph C. Fjelstad ,  William F. Wiedemann ,  Para K. Segaram ,  Kevin P. Grundy

Inventor： Gary Yasumura ,  Joseph C. Fjelstad ,  William F. Wiedemann ,  Para K. Segaram ,  Kevin P. Grundy

IPC: H01R12/00

CPC classification number: H05K1/117 ,  H01R12/523 ,  H01R12/62 ,  H01R12/716 ,  H01R13/24 ,  H01R13/6587 ,  H05K1/142 ,  H05K3/366 ,  H05K3/368 ,  H05K2201/09063 ,  H05K2201/09445 ,  H05K2201/09472 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2203/167

Abstract: An electrical connector comprised of a plurality of electrical contacts arranged in a stair-step configuration designed to mate with electrical components having electrical contacts arranged in a stair-step configuration. A direct connect signaling system comprised of stair-step electrical connectors mated to stair-step printed circuit boards, other stair-step electrical components, or combinations thereof.

Abstract translation: 一种电连接器，包括布置成阶梯式结构的多个电触点，其设计成与具有以阶梯状构造布置的电触点的电气部件配合。 一种直接连接信号系统，包括与台阶式印刷电路板，其他楼梯电气部件或其组合配合的楼梯级电连接器。

公开(公告)号：US20100147560A1

公开(公告)日：2010-06-17

申请号：US12628281

申请日：2009-12-01

Applicant: Kentaro KANEKO

Inventor： Kentaro KANEKO

IPC: H05K1/02 ,  B32B37/00

CPC classification number: H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1058 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/205 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/10674 ,  H05K2203/0369 ,  H05K2203/0376 ,  Y10T156/10 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A wiring board (package) includes: a cavity formed at a position corresponding to a chip mounting area of the outermost insulating layer on one side of both surfaces of the wiring board; a pad exposed from the surface of the insulating layer in the cavity; and a pad exposed from the surface of the insulating layer in a peripheral region of the cavity. A chip is flip-chip bonded to the pads in the cavity of the package, and another package is bonded to the pads in the peripheral region of the cavity, to thereby form a semiconductor device having a package on package (POP) structure.

Abstract translation: 布线板（封装）包括：形成在与布线板的两面的一侧的最外层绝缘层的芯片安装区域对应的位置的空腔; 从空腔中的绝缘层的表面暴露的焊盘; 以及在空腔的周边区域中从绝缘层的表面暴露的焊盘。 将芯片倒装芯片结合到封装空腔中的焊盘，另一个封装结合到空腔周边区域中的焊盘，从而形成具有封装封装（POP）结构的半导体器件。