公开(公告)号：US09171777B2

公开(公告)日：2015-10-27

申请号：US13752670

申请日：2013-01-29

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Vanessa Capodieci ,  Markus Dinkel ,  Uwe Schmalzbauer

IPC: H01L23/48 ,  H01L23/58 ,  H01L21/66

CPC classification number: H01L27/0207 ,  G01R31/26 ,  H01L22/34 ,  H01L23/13 ,  H01L23/48 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/40 ,  H01L29/407 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括具有多边形几何形状的主表面和在半导体衬底上的主区域内制造的主电路。 主电路可操作以执行电主功能。 主区域在半导体衬底的主表面上延伸，在半导体衬底的主表面的多边形几何形状的拐角处打开至少一个拐角区域。 拐角区域从角部开始沿着半导体衬底的边缘延伸至少300μm。

公开(公告)号：US09165921B2

公开(公告)日：2015-10-20

申请号：US13716784

申请日：2012-12-17

Applicant: Infineon Technologies AG

Inventor： Peter Nelle ,  Markus Zundel

IPC: H01L29/78 ,  H01L27/06

CPC classification number: H01L29/7808 ,  H01L27/0629 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7813 ,  H01L29/8613

Abstract: One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of transistor cells in a semiconductor body. A width w3 of a transistor mesa region of each of the plurality of transistor cells and a width w1 of a first trench of each of the plurality of transistor cells satisfy the following relationship: w3

Abstract translation: 半导体器件的一个实施例包括致密沟槽晶体管单元阵列。 密集沟槽晶体管单元阵列包括半导体本体中的多个晶体管单元。 多个晶体管单元的晶体管台面区域的宽度w3和多个晶体管单元中的每一个的第一沟槽的宽度w1满足以下关系：w3 <1.5×w1。 半导体器件还包括半导体二极管。 至少一个半导体二极管布置在多个晶体管单元的第一和第二部分之间，并且包括邻接第二沟槽的相对壁的二极管台面区域。 第一沟槽的深度d1和第二沟槽的深度d2相差至少20％。

公开(公告)号：US20150137224A1

公开(公告)日：2015-05-21

申请号：US14082491

申请日：2013-11-18

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体本体中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，电连接到源极区的源极接触，电连接到漏极区的漏极接触，以及沟道区处的栅电极。 沟道区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 通道区域具有沿着第一方向延伸的第一脊的形状。 源极接触和漏极接触中的一个与第一主表面相邻，源极接触和漏极接触中的另一个与与第一主表面相对的第二主表面相邻。

公开(公告)号：US20150069394A1

公开(公告)日：2015-03-12

申请号：US14020117

申请日：2013-09-06

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Thomas Ostermann

IPC: H01L23/544 ,  H01L29/06 ,  H01L21/66

CPC classification number: H01L23/544 ,  H01L21/784 ,  H01L22/12 ,  H01L22/34 ,  H01L29/0657 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00 ,  H01L2224/03

Abstract: A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line.

Abstract translation: 一种器件包括半导体芯片。 半导体芯片的前端的轮廓包括以大于90°的内角连接的两条线段和弧形线的折线。

公开(公告)号：US20140299972A1

公开(公告)日：2014-10-09

申请号：US14249642

申请日：2014-04-10

Applicant: Infineon Technologies AG

Inventor： Hermann Gruber ,  Thomas Gross ,  Andreas Peter Meiser ,  Markus Zundel

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76898 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a first side and a second side opposite the first side, an active area and a through contact area, the active area including a transistor structure having a control electrode, the through contact area including a semiconductor mesa having insulated sidewalls. The semiconductor device further includes a first metallization on the first side in the active area and a recess extending from the first side into the semiconductor substrate and between the active area and the through contact area and including in the through contact area a horizontally widening portion, the recess being at least partly filled with a conductive material forming a first conductive region in ohmic contact with the semiconductor mesa and the transistor structure. The semiconductor device also includes a control metallization on the second side and in ohmic contact with the semiconductor mesa.

Abstract translation: 半导体器件包括具有第一侧和与第一侧相对的第二侧的半导体衬底，有源区和贯通接触区，所述有源区包括具有控制电极的晶体管结构，所述贯通接触区包括半导体台面，所述半导体衬底具有 绝缘侧壁。 所述半导体器件还包括在所述有源区域中的第一侧上的第一金属化和从所述第一侧延伸到所述半导体衬底中以及在所述有源区域和所述贯穿接触区域之间并且在所述贯穿接触区域中包括水平扩大部分的凹部， 所述凹部至少部分地填充有形成与所述半导体台面和所述晶体管结构欧姆接触的第一导电区域的导电材料。 半导体器件还包括在第二侧上的控制金属化并与半导体台面欧姆接触。

公开(公告)号：US20140167043A1

公开(公告)日：2014-06-19

申请号：US13719599

申请日：2012-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Markus Zundel ,  Vanessa Capodieci ,  Markus Dinkel ,  Uwe Schmalzbauer

IPC: H01L23/48 ,  H01L21/02 ,  H01L23/544

CPC classification number: H01L23/48 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括具有多边形几何形状的主表面和在半导体衬底上的主区域内制造的主电路。 主电路可操作以执行电主功能。 主区域在半导体衬底的主表面上延伸，在半导体衬底的主表面的多边形几何形状的拐角处打开至少一个拐角区域。 拐角区域从角部开始沿着半导体衬底的边缘延伸至少300μm。

公开(公告)号：US20140097431A1

公开(公告)日：2014-04-10

申请号：US14055982

申请日：2013-10-17

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler ,  Peter Nelle ,  Ludger Borucki ,  Markus Winkler ,  Erwin Vogl

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential.

Abstract translation: 根据各种实施例的用于处理半导体器件的方法可以包括：提供具有第一焊盘和与第一焊盘电连接的第二焊盘的半导体器件; 对所述第一焊盘和所述第二焊盘中的至少一个施加至少一个电测试电位; 以及在施加所述至少一个电测试电位之后将所述第一焊盘和所述第二焊盘彼此电连接。

公开(公告)号：US20140077262A1

公开(公告)日：2014-03-20

申请号：US14032437

申请日：2013-09-20

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Gabriela Brase ,  Peter Nelle ,  Guenther Schindler

IPC: H01L29/739

CPC classification number: H01L29/7393 ,  H01L23/3178 ,  H01L23/3192 ,  H01L29/0657 ,  H01L29/407 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.

Abstract translation: 本发明涉及半导体元件，其包括半导体本体，半导体主体上的绝缘体和至少部分地布置在半导体本体内的电池阵列。 电池阵列具有至少一个p-n结和至少一个接触连接。 绝缘体通过周向扩散阻挡层在半导体主体的横向方向上界定。

公开(公告)号：US20140048871A1

公开(公告)日：2014-02-20

申请号：US13933047

申请日：2013-07-01

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler ,  Norbert Krischke

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/743 ,  H01L27/0733 ,  H01L28/40 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/945

Abstract: A semiconductor component arrangement includes a semiconductor body, a transistor structure, a further component, and at least a first electrode structure. The semiconductor body has a first side and a second side. The transistor structure is integrated in the semiconductor body, and includes a source and a drain. The further component is also integrated in the semiconductor body. The first electrode structure is disposed in at least a first trench, and includes at least one electrode. The first electrode structure electrically connects at least one of the source and the drain to the further component.

Abstract translation: 半导体元件布置包括半导体本体，晶体管结构，另外的元件以及至少第一电极结构。 半导体本体具有第一面和第二面。 晶体管结构集成在半导体本体中，并且包括源极和漏极。 另外的部件也集成在半导体本体中。 第一电极结构设置在至少第一沟槽中，并且包括至少一个电极。 第一电极结构将源极和漏极中的至少一个电连接到另一个部件。

公开(公告)号：US11804432B2

公开(公告)日：2023-10-31

申请号：US17173863

申请日：2021-02-11

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Sergey Ananiev ,  Andreas Behrendt ,  Holger Doepke ,  Uwe Schmalzbauer ,  Michael Sorger ,  Dominic Thurmer

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76825 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.