公开(公告)号：US08065795B2

公开(公告)日：2011-11-29

申请号：US11760217

申请日：2007-06-08

Applicant: Kevin C. Olson ,  Alan G. Wang

Inventor： Kevin C. Olson ,  Alan G. Wang

IPC: H01K3/22

CPC classification number: H01L21/486 ,  C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/142 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  H01L2924/00

Abstract: Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

Abstract translation: 提供了用于制造多层电路组件的工艺和通过这些工艺制造的多层电路组件。 该方法包括（a）提供基底，其至少一个区域包括多个通孔，这些区域的通孔密度为500至10,000个孔/平方英寸（75至1550个孔/平方厘米）; （b）将介电涂层施加到所述基底的所有暴露表面上以在其上形成保形涂层; 和（c）在基片的所有表面上涂一层金属。 可以包括诸如电路化的附加处理步骤。

公开(公告)号：US20110206909A1

公开(公告)日：2011-08-25

申请号：US13125811

申请日：2009-10-29

Applicant: Ofer Sneh

Inventor： Ofer Sneh

IPC: B32B15/04 ,  C23C16/40 ,  B32B3/10 ,  C09D7/00

CPC classification number: H05K3/28 ,  C23C16/45529 ,  C23C16/45555 ,  H05K3/244 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/0769 ,  Y10T428/24802 ,  Y10T428/31678

Abstract: A coating is formed by depositing the coating on a metallic feature at a deposition temperature. Subsequently, the deposited coating and the metallic feature are cooled below the deposition temperature. The coating is chosen such that this cooling step causes the coating to induce a tensile stress in the metallic feature sufficient to substantially suppress the growth of metallic whiskers on that metallic feature. The coating thereby acts to suppress the growth of metallic whiskers.

Abstract translation: 通过在沉积温度下将涂层沉积在金属特征上形成涂层。 随后，沉积的涂层和金属特征被冷却到沉积温度以下。 选择涂层使得该冷却步骤使涂层在金属特征中引起足够的拉伸应力，以足以基本上抑制该金属特征上的金属晶须的生长。 因此，涂层起到抑制金属须晶生长的作用。

公开(公告)号：US07982139B2

公开(公告)日：2011-07-19

申请号：US11356350

申请日：2006-02-17

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic. With this structure, the static capacitance of the layered capacitor portion 40 can be high, and an adequate decoupling effect is exhibited even under circumstances in which instantaneous potential drops occur readily.

Abstract translation: 多层印刷电路板10包括：安装部分60，其顶表面上安装有电连接到布线图案32的半导体元件; 以及具有由陶瓷形成的高介电常数层43的电容器部分40和夹在高介电常数层43上的第一和第二层电极41和42。第一和第二层电极41和42中的一个连接到 半导体元件的电源线和第一和第二层电极41和42中的另一个连接到接地线。 在这种多层印刷电路板10中，连接在电源线和接地线之间的层状电容器部分40中包括的高介电常数层43由陶瓷形成。 利用这种结构，层状电容器部分40的静态电容可以很高，并且即使在容易发生瞬时电位下降的情况下也可以发挥足够的去耦效应。

公开(公告)号：US07927517B2

公开(公告)日：2011-04-19

申请号：US12437657

申请日：2009-05-08

Applicant: Jun Hee Bae ,  Seung Hyun Kim ,  Yul Kyo Chung ,  Won Hoon Song ,  Sung Taek Lim ,  Hyun Ju Jin

Inventor： Jun Hee Bae ,  Seung Hyun Kim ,  Yul Kyo Chung ,  Won Hoon Song ,  Sung Taek Lim ,  Hyun Ju Jin

IPC: C09D5/24 ,  H01B1/08

CPC classification number: H01L21/02282 ,  H01G4/1218 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/316 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179

Abstract: Disclosed herein are a coating solution for the formation of a dielectric thin film and a method for the formation of a dielectric thin film using the coating solution. The coating solution comprises a titanium alkoxide, a β-diketone or its derivative, and a benzoic acid derivative having an electron donating group. The method comprises spin coating the coating solution on a substrate to form a thin film and drying the thin film at a low temperature to crystallize the thin film. The titanium-containing coating solution is highly stable. In addition, the coating solution enables formation of a thin film, regardless of the kind of substrates, and can be used to form dielectric thin films in an in-line mode in the production processes of PCBs.

Abstract translation: 本文公开了用于形成电介质薄膜的涂布溶液和使用该涂布溶液形成电介质薄膜的方法。 涂层溶液包含烷氧基钛，二 - 二酮或其衍生物，以及具有给电子基团的苯甲酸衍生物。 该方法包括将涂布溶液旋涂在基材上以形成薄膜，并在低温下干燥薄膜以使薄膜结晶。 含钛涂层溶液高度稳定。 此外，涂布溶液能够形成薄膜，而不管基板的种类如何，并且可以用于在PCB的生产过程中以在线模式形成电介质薄膜。

公开(公告)号：US07888803B2

公开(公告)日：2011-02-15

申请号：US11580928

申请日：2006-10-16

Applicant: Takashi Kariya ,  Hironori Tanaka

Inventor： Takashi Kariya ,  Hironori Tanaka

IPC: H01L23/48

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09827 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2224/05599

Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.

Abstract translation: 一种印刷电路板，包括导体部分，在导体部分上形成的绝缘层，形成在绝缘层之上的薄膜电容器，并且包括第一电极，第二电极和介于第一电极和第二电极之间的高电介质层 第二电极和通过第二电极和绝缘层形成的通孔导体结构，并且电连接第二电极和导体部分。 通孔导体结构在第二电极中具有第一部分，在绝缘层中具有第二部分。 通孔导体结构的第一部分具有朝向导体部分逐渐变细的截锥形。

公开(公告)号：US20110012697A1

公开(公告)日：2011-01-20

申请号：US12922307

申请日：2009-04-22

Applicant: Koichi Takemura ,  Noriaki Ando ,  Tsuneo Tsukagoshi

Inventor： Koichi Takemura ,  Noriaki Ando ,  Tsuneo Tsukagoshi

IPC: H01P1/203 ,  H05K13/00

CPC classification number: H01P1/203 ,  H01P1/2005 ,  H01P11/007 ,  H01Q15/008 ,  H05K1/0236 ,  H05K2201/0179 ,  H05K2201/09309 ,  H05K2201/09627 ,  Y10T29/49117

Abstract: An electromagnetic bandgap structure EBG includes a rigid substrate, a first conductive plane provided on the rigid substrate, a dielectric layer provided on the first conductive plane, and a plurality of conductor patches arrayed in a two-dimensional regular pattern on the dielectric layer. The electromagnetic bandgap structure also includes an interlayer insulation film provided on top of the conductor patches, and a second conductive plane provided on the interlayer insulation film. The conductor patches and the second conductive plane are interconnected by a plurality of conductors provided in extending through the bulk of the interlayer insulation film.

Abstract translation: 电磁带隙结构EBG包括刚性基板，设置在刚性基板上的第一导电平面，设置在第一导电平面上的电介质层，以及在电介质层上以二维规则图案排列的多个导体贴片。 电磁带隙结构还包括设置在导体贴片顶部的层间绝缘膜和设置在层间绝缘膜上的第二导电平面。 导体贴片和第二导电平面通过延伸穿过层间绝缘膜主体的多个导体互连。

公开(公告)号：US07863706B2

公开(公告)日：2011-01-04

申请号：US11770690

申请日：2007-06-28

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L29/00

CPC classification number: H01L27/016 ,  H01L21/77 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09845

Abstract: A circuit system includes: forming a first electrode over a substrate; applying a dielectric layer over the first electrode and the substrate; forming a second electrode over the dielectric layer; and forming a dielectric structure from the dielectric layer with the dielectric structure within a first horizontal boundary of the first electrode.

Abstract translation: 电路系统包括：在衬底上形成第一电极; 在第一电极和衬底上施加电介质层; 在所述电介质层上形成第二电极; 以及在所述第一电极的第一水平边界内从具有所述电介质结构的介电层形成电介质结构。

公开(公告)号：US07687366B2

公开(公告)日：2010-03-30

申请号：US11601101

申请日：2006-11-17

Applicant: Yongki Min

Inventor： Yongki Min

IPC: H01L21/20 ,  H01G9/00

CPC classification number: H01L23/49822 ,  H01G4/228 ,  H01G4/33 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K1/162 ,  H05K3/048 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09763 ,  Y10T29/417 ,  H01L2924/00

Abstract: An embedded passive structure, its method of formation, and its integration onto a substrate during fabrication are disclosed. In one embodiment, the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower electrode layers are patterned in such a way as to reduce damage and improve cycle time. In one embodiment, the capacitor dielectric has a high dielectric constant and the substrate is an organic packaging substrate.

Abstract translation: 公开了嵌入式被动结构，其形成方法及其在制造过程中与衬底的集成。 在一个实施例中，嵌入式无源结构是使用已经安装在基板上的薄膜层叠体形成的薄膜电容器（TFC）。 TFC的电容器电介质和/或下电极层被图案化以减少损坏并改善循环时间。 在一个实施例中，电容器电介质具有高介电常数，并且衬底是有机封装衬底。

公开(公告)号：US20100051328A1

公开(公告)日：2010-03-04

申请号：US12258453

申请日：2008-10-27

Applicant: Ra-Min Tain ,  Ming-Ji Dai

Inventor： Ra-Min Tain ,  Ming-Ji Dai

IPC: H05K1/03 ,  B05D5/12 ,  H05K1/02 ,  H05K1/00

CPC classification number: H05K1/053 ,  B82Y10/00 ,  H05K2201/0179 ,  H05K2201/0209 ,  H05K2201/0251 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2203/025

Abstract: A circuit board structure and a manufacturing method thereof are provided. The circuit board structure includes a composite substrate, a dielectric layer, and a circuit layer. The composite substrate includes a metal substrate doped with non-metal powders and a metal buffer layer. A surface of the metal buffer layer opposite to the other surface of the metal buffer layer in contact with the metal substrate is treated by a polishing process. The dielectric layer is formed on the polished surface of the metal buffer layer, and the circuit layer is formed on the dielectric layer. Alternatively, a barrier layer is interposed between the dielectric layer and the metal buffer layer for preventing a diffusion effect of the metal buffer layer.

Abstract translation: 提供一种电路板结构及其制造方法。 电路板结构包括复合衬底，电介质层和电路层。 复合衬底包括掺杂有非金属粉末和金属缓冲层的金属衬底。 通过抛光处理处理与金属基板接触的金属缓冲层的另一表面相对的金属缓冲层的表面。 电介质层形成在金属缓冲层的抛光表面上，电介质层形成在电介质层上。 或者，在电介质层和金属缓冲层之间插入阻挡层，以防止金属缓冲层的扩散效应。

公开(公告)号：US07638714B2

公开(公告)日：2009-12-29

申请号：US11969485

申请日：2008-01-04

Applicant: Yu-Hsueh Lin

Inventor： Yu-Hsueh Lin

IPC: H05K1/00

CPC classification number: H05K7/205 ,  H01L23/3732 ,  H01L2924/0002 ,  H05K1/053 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0323 ,  H05K2203/0315 ,  H01L2924/00

Abstract: A method for manufacturing a substrate board with high efficiency of heat conduction and electrical isolation is disclosed. The method comprises the steps of: providing a substrate layer with an arrangement surface and a heat-dissipating surface; executing an anodic treatment on the arrangement surface and the heat-dissipating surface to respectively form a first anodic treatment layer and a second anodic treatment layer; forming a heat conduction and electrical isolation layer on the second anodic treatment layer; and forming a diamond like carbon (DLC) layer on the heat conduction and electrical isolation layer. The heat expansion coefficient of the substrate layer is greater than that of the second anodic treatment layer, the heat conduction and electrical isolation layer, and the DLC layer in turn.

Abstract translation: 公开了一种用于制造具有高效率的热传导和电隔离的基板的方法。 该方法包括以下步骤：为衬底层提供布置表面和散热表面; 对配置面和散热面进行阳极处理，分别形成第一阳极处理层和第二阳极处理层; 在所述第二阳极处理层上形成导热和电隔离层; 并在导热和电隔离层上形成类金刚石碳（DLC）层。 衬底层的热膨胀系数大于第二阳极处理层，热传导和电隔离层以及DLC层的热膨胀系数。