公开(公告)号：US07983051B2

公开(公告)日：2011-07-19

申请号：US12100023

申请日：2008-04-09

Applicant: Jiunn-Chung Lee ,  Chien-Chung Huang

Inventor： Jiunn-Chung Lee ,  Chien-Chung Huang

IPC: H05K1/00

CPC classification number: H05K1/181 ,  G11C5/00 ,  H05K2201/09254 ,  H05K2201/10159 ,  H05K2201/10189 ,  Y02P70/611

Abstract: A dynamic radon access memory (DRAM) module includes a printed circuit board, a number of DRAM units, a number of flash memory units, a number connecting pins and an interface controller. The DRAM units and the flash memory units are distributed on the printed circuit board. The connecting pins are formed at an edge of the printed circuit board. The interface controller is electrically connected to the flash memory units and a portion of the connecting pins, wherein each of the interface controller provides at least one serial interface between the flash memory units and the portion of connecting pins thereby enabling data transmission through the portion of connecting pins in at least one serial mode. The flash memory units integrally constitute a flash disk drive in the DRAM module. Therefore, frequently installation and uninstallation of the flash memory drive can be avoided. A motherboard assembly including the aforementioned DRAM module can be developed.

Abstract translation: 动态氡存取存储器（DRAM）模块包括印刷电路板，多个DRAM单元，多个闪存单元，数字连接引脚和接口控制器。 DRAM单元和闪存单元分布在印刷电路板上。 连接销形成在印刷电路板的边缘。 接口控制器电连接到闪存单元和连接引脚的一部分，其中每个接口控制器在闪存单元和连接引脚的部分之间提供至少一个串行接口，从而使数据可以通过 在至少一个串行模式下连接引脚。 闪存单元一体地构成DRAM模块中的闪存盘驱动器。 因此，可以避免闪存驱动器的频繁安装和卸载。 可以开发包括上述DRAM模块的主板组件。

公开(公告)号：US07952229B2

公开(公告)日：2011-05-31

申请号：US12393994

申请日：2009-02-26

Applicant: Yi-Chang Lu ,  Cheng-Hung Li ,  Chung-Yui Kuo ,  Tsung-Yu Wu

Inventor： Yi-Chang Lu ,  Cheng-Hung Li ,  Chung-Yui Kuo ,  Tsung-Yu Wu

IPC: H05K1/02

CPC classification number: H02J1/06 ,  H05K1/0265 ,  H05K2201/09254 ,  H05K2201/09727 ,  H05K2201/0979 ,  Y10T307/492

Abstract: A power distribution system is disclosed. The system includes a first power line and a second power line laid out on a substrate. The first power line is spaced apart from the second power line. The system also includes at least one conductive connecting line that electrically couples the first power line at one end and the second power line at another end. A power supply supplies power to the first power line and the second power line. A supply node on the conductive connecting line is then used to provide the supplied power.

Abstract translation: 公开了配电系统。 该系统包括布置在基板上的第一电源线和第二电源线。 第一电力线与第二电力线隔开。 该系统还包括至少一个导电连接线，其在一端电耦合第一电力线和在另一端电耦合第二电力线。 电源为第一电力线和第二电力线供电。 然后使用导电连接线上的供电节点来提供所供电的电力。

公开(公告)号：US20110115495A1

公开(公告)日：2011-05-19

申请号：US12887128

申请日：2010-09-21

Applicant: Tadahiro KUNII

Inventor： Tadahiro KUNII

IPC: G01R31/02 ,  H02H3/22

CPC classification number: H05K1/0254 ,  G01R31/1236 ,  H05K1/0215 ,  H05K3/222 ,  H05K3/3457 ,  H05K2201/09254 ,  H05K2201/10409

Abstract: A communication apparatus including: a frame; a transmission line connectable to a public line network; a print circuit board including a frame ground terminal portion and configured such that a dielectric strength between the transmission line and the frame ground terminal portion takes a specific value in a state in which elements are connected to between the transmission line and the frame ground terminal portion via conductor patterns. The frame ground terminal portion includes: a first land formed on a first conductor pattern formed on a face of the print circuit board, a surge protection element being connected to the first conductor pattern; and a second land formed on a second conductor pattern formed on the face, elements different from the surge protection element being connected to the second conductor pattern. The first and second lands contacts the frame by fixing of the print circuit board to the frame.

Abstract translation: 一种通信装置，包括：帧; 可连接到公共线网络的传输线; 印刷电路板，包括框架接地端子部分，并且构造成使得传输线和框架接地端子部分之间的介电强度在元件连接到传输线和框架接地端子部分之间的状态下具有特定值 通过导体图案。 框架接地端子部分包括：形成在形成在印刷电路板的表面上的第一导体图案上的第一焊盘;浪涌保护元件，连接到第一导体图案; 以及形成在形成在所述面上的第二导体图案上的第二平台，与所述浪涌保护元件不同的元件连接到所述第二导体图案。 通过将印刷电路板固定到框架上，第一和第二平台接触框架。

公开(公告)号：US07889510B2

公开(公告)日：2011-02-15

申请号：US11797206

申请日：2007-05-01

Applicant: Satoshi Takeuchi ,  Hiroki Kamiya ,  Katsunori Kubota ,  Motoki Shimizu

Inventor： Satoshi Takeuchi ,  Hiroki Kamiya ,  Katsunori Kubota ,  Motoki Shimizu

IPC: H05K1/18

CPC classification number: G01R31/2818 ,  G01R31/2812 ,  H05K1/0268 ,  H05K1/186 ,  H05K3/4614 ,  H05K3/4617 ,  H05K2201/0394 ,  H05K2201/09254 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611

Abstract: A component-embedded board device has a wiring board in which an electronic component is embedded, a connection member which is conductive and arranged at a surface of the wiring board, and an inner wiring unit which is arranged in the wiring board and connects an electrode of the electronic component with the connection member. The component-embedded board device is further provided with an inspection connection member for an inspection of a faulty wiring of the inner wiring unit, and an inspection wiring unit which is arranged in the wiring board and connects the inspection connection member with one of the electrode and a predetermined portion of the inner wiring unit. The inspection connection member is conductive and arranged at a surface of the wiring board.

Abstract translation: 组件嵌入式板装置具有嵌入有电子部件的布线基板，导电性配置在配线基板的表面的连接部件和配置在配线基板上的内部配线部， 的电子部件。 组件嵌入式板装置还具有用于检查内部布线单元的故障布线的检查连接构件和布置在布线板中并将检查连接构件与电极之一连接的检查布线单元 和内部布线单元的预定部分。 检查连接构件是导电的并且布置在布线板的表面上。

公开(公告)号：US20100264947A1

公开(公告)日：2010-10-21

申请号：US12763907

申请日：2010-04-20

Applicant: Charles A. Miller ,  John Matthew Long

Inventor： Charles A. Miller ,  John Matthew Long

IPC: G01R31/02

CPC classification number: G01R31/31926 ,  G01R1/07378 ,  G01R31/318511 ,  G11C29/56 ,  G11C2029/2602 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0289 ,  H05K2201/09254 ,  Y10T29/49117

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

Abstract translation: 互连结构采用闭合栅格总线将集成电路测试器通道连接到半导体晶片上的输入/输出（I / O）焊盘阵列，使得测试仪通道可以同时与所有I / O焊盘通信。 互连结构包括实现总线节点阵列的电路板，每个总线节点对应于单独的一个I / O焊盘。 电路板包括至少两层。 安装在第一层上的轨迹形成一组第一个菊花链总线，每个链路总线连接总线节点阵列的单独行的所有总线节点。 安装在第二电路板层上的迹线形成一组第二菊花链总线，每条链路总线连接总线节点阵列的单独列的所有总线节点。 第一和第二菊花链总线的通路和其他电路板互连端，使得它们形成闭合栅格总线。 每个总线节点通过单独的隔离电阻器连接到安装在电路板表面上的单独的接触焊盘。 一组弹簧触点或探针将每个接触垫连接到晶片上的单独的I / O焊盘之间。

公开(公告)号：US20100242259A1

公开(公告)日：2010-09-30

申请号：US12795613

申请日：2010-06-07

Applicant: Kumiko Kaneko

Inventor： Kumiko Kaneko

IPC: G01R31/28

CPC classification number: G01R31/2818 ,  H05K1/0268 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09254 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/166 ,  Y10T29/49004

Abstract: An electronic module capable of easily determining connection reliability of an ACF connection portion is provided. Electrode wirings of a board serving as an electronic parts of a display panel are connected with ACF bonding wirings of an FPC through an ACF to make electrical connection between the FPC and the board. Two branch portions branched from each of the ACF bonding wirings extend to an edge of the FPC. Low resistance measurement of the connection portion can be performed using the electrode wiring of the board and the branch portions, so whether or not the ACF connection portion is faulty can be determined.

Abstract translation: 提供了能够容易地确定ACF连接部的连接可靠性的电子模块。 用作显示面板的电子部件的板的电极布线通过ACF与FPC的ACF接合布线连接，以在FPC和板之间进行电连接。 从每个ACF接合布线分支的两个分支部分延伸到FPC的边缘。 可以使用电路板和分支部分的电极布线来实现连接部分的低电阻测量，因此可以确定ACF连接部分是否有故障。

公开(公告)号：US07800913B2

公开(公告)日：2010-09-21

申请号：US11539706

申请日：2006-10-09

Applicant: Michiharu Torii ,  Kouichi Nagao ,  Nozomi Shimoishizaka

Inventor： Michiharu Torii ,  Kouichi Nagao ,  Nozomi Shimoishizaka

IPC: H05K1/00

CPC classification number: H05K1/0271 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09254 ,  H05K2201/09781 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A wiring board includes: a flexible insulating base; a plurality of conductive wirings arranged on the insulating base, end portions of the conductive wirings defining inner leads at a region where a semiconductor chip is to be mounted; and bump electrodes that are provided respectively at the inner leads of the conductive wirings. The wiring board further includes: dummy inner leads having a shape and a pitch corresponding to a shape and a pitch of the inner leads and aligned with the inner leads, the dummy inner leads being provided with dummy bump electrodes corresponding to the bump electrodes; a trunk conductive wiring provided for a group of one or an adjacent plurality of the dummy inner leads; and a branch wiring branching off from the trunk conductive wiring, the branch wiring being connected with the dummy inner leads belonging to the group corresponding to the trunk conductive wiring. Stress concentration on the inner leads during packaging of the semiconductor chip, resulting from the sparse arrangement of the electrode pads of the semiconductor chip, can be alleviated, thus suppressing a break in the inner leads.

Abstract translation: 布线板包括：柔性绝缘基底; 布置在所述绝缘基底上的多个导电布线，所述导电布线的端部在要安装半导体芯片的区域处限定内引线; 以及分别设置在导电布线的内引线处的凸起电极。 布线板还包括：虚拟内引线，具有与内引线的形状和间距对应的形状和间距，并与内引线对准，虚拟内引线设置有与突起电极对应的虚设凸起电极; 为一组或相邻的多个虚拟内引线设置的躯干导电布线; 以及从所述主干导电布线分支的分支布线，所述分支布线与属于与所述导体布线对应的组的所述虚拟内部引线连接。 可以减轻由半导体芯片的电极焊盘的稀疏布置导致的半导体芯片封装期间的内部引线上的应力集中，从而抑制内部引线的断裂。

公开(公告)号：US20100116540A1

公开(公告)日：2010-05-13

申请号：US12611261

申请日：2009-11-03

Applicant: Jun ISHII ,  Toshiki NAITOU ,  Mitsuru HONJO

Inventor： Jun ISHII ,  Toshiki NAITOU ,  Mitsuru HONJO

IPC: H05K1/11 ,  B05D5/12

CPC classification number: H05K3/4685 ,  G11B5/484 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0265 ,  H05K1/056 ,  H05K3/06 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/0323 ,  Y10T29/49155

Abstract: An end of a first line and an end of a second line of a first write wiring pattern are arranged on both sides of a third line of a second write wiring pattern. Circular connection portions are provided at the ends of the first line and the second line. In addition, through holes are formed in respective portions of a base insulating layer below the connection portions. Each connection portion comes in contact with a connecting region of a suspension body within the through hole.

Abstract translation: 第一写入布线图案的第一行的一端和第二行的末端布置在第二写入布线图案的第三行的两侧。 圆形连接部设置在第一线和第二线的端部。 此外，在连接部分下方的基底绝缘层的各个部分中形成通孔。 每个连接部分与通孔内的悬架体的连接区域接触。

公开(公告)号：US07675729B2

公开(公告)日：2010-03-09

申请号：US10582758

申请日：2004-12-22

Applicant: David Anthony ,  Anthony Anthony ,  William M. Anthony ,  James Muccioli ,  Richard A. Neifeld

Inventor： David Anthony ,  Anthony Anthony ,  William M. Anthony ,  James Muccioli ,  Richard A. Neifeld

IPC: H02H9/00

CPC classification number: H01G4/35 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H05K1/0233 ,  H05K2201/09254 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/1006 ,  H05K2201/10454 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An energy conditioner structure comprising a first electrode (120), a second electrode (80), and a shield structure (70, 110, 150) provides improved energy conditioning in electrical circuits. The structures may exist as discrete components or part of an integrated circuit. The shield structure in the energy conditioner structure does not electrically connect to any circuit element.

Abstract translation: 包括第一电极（120），第二电极（80）和屏蔽结构（70,110,150）的能量调节器结构在电路中提供改进的能量调节。 结构可以作为分立组件或集成电路的一部分存在。 能量调节器结构中的屏蔽结构不电连接到任何电路元件。

公开(公告)号：US20100038118A1

公开(公告)日：2010-02-18

申请号：US12191645

申请日：2008-08-14

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H05K1/02

CPC classification number: H05K3/242 ,  H05K3/0052 ,  H05K2201/09254

Abstract: A substrate panel primarily comprises a plurality of substrate strips arranged in an array, one or more current input lines, a plurality of cascaded lines connecting between the substrate strips, and a current input buffer gate. Current input lines connect a current input side of the substrate panel to the adjacent substrate strips. The current input buffer gate has a frame around the substrate strips and a plurality of meshes where the frame intersects with the current input lines and the meshes intersect with the cascaded lines with both ends of the meshes connecting to the frame. Therefore, the current can be evenly distributed to each substrate strip during plating processes to improve the issues of different plating thicknesses and different plating roughness caused by different current densities and to protect the internal circuits inside the substrate strips from the damages due to current surges and unstable voltages.

Abstract translation: 衬底面板主要包括布置成阵列的多个衬底条，一个或多个电流输入线，连接在衬底条之间的多条级联线和电流输入缓冲门。 电流输入线将基板面板的电流输入侧连接到相邻的基板条。 当前输入缓冲器门具有围绕衬底条的框架以及框架与当前输入线相交的多个网格，并且网格与连接到框架的网格的两端的级联线相交。 因此，电镀过程中电流可以均匀地分布到每个衬底条上，以改善由不同电流密度引起的不同电镀厚度和不同电镀粗糙度的问题，并保护衬底条内部的电路免受由于电流浪涌引起的损坏， 电压不稳定