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21.发明申请公开(公告)号：US20180116051A1
公开(公告)日：2018-04-26
申请号：US15847852
申请日：2017-12-19
Applicant: MEDIATEK INC.
Inventor： Sheng-Ming Chang , Chia-Hui Liu , Shih-Chieh Lin , Chun-Ping Chen
CPC classification number: H05K1/115 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H05K1/0262 , H05K1/0298 , H05K1/05 , H05K1/111 , H05K1/114 , H05K1/181 , H05K2201/09227 , H05K2201/095 , H05K2201/09509 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00012 , H01L2924/00
Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.
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公开(公告)号：US09867290B2
公开(公告)日：2018-01-09
申请号：US14834205
申请日：2015-08-24
Applicant: Multek Technologies Ltd.
Inventor： Kwan Pen , Pui Yin Yu
CPC classification number: H05K1/115 , H05K1/0216 , H05K1/0298 , H05K1/112 , H05K3/0058 , H05K3/06 , H05K3/181 , H05K3/188 , H05K3/42 , H05K3/422 , H05K3/424 , H05K3/429 , H05K3/4602 , H05K3/4623 , H05K3/4638 , H05K2201/095 , H05K2201/09545 , H05K2201/09554 , H05K2201/10303
Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.
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公开(公告)号：US09844130B2
公开(公告)日：2017-12-12
申请号：US15391053
申请日：2016-12-27
Inventor： Takumi Ikeda , Masao Kainuma , Yasuyuki Kimura , Chang Hun Gang , Tae Uk Gang , Hyung Gon Kim
CPC classification number: H05K1/0274 , H01L31/02005 , H01L31/0203 , H01S5/02256 , H01S5/18 , H05K1/115 , H05K2201/095
Abstract: A package for an optical semiconductor device includes an eyelet, a signal lead inserted in a through hole formed in the eyelet, and sealing glass sealing the signal lead in the through hole. The signal lead includes a first portion, a second portion and a third portion that are greater in diameter than the first portion and on opposite sides of the first portion, a first tapered portion extending from the second portion to the first portion, and a second tapered portion extending from the third portion to the first portion. The first portion and the first and second tapered portions are buried in the sealing glass. The total length of a part of the second portion in the sealing glass and a part of the third portion in the sealing glass is 0.2 mm or less.
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公开(公告)号：US09832888B1
公开(公告)日：2017-11-28
申请号：US15191554
申请日：2016-06-24
Applicant: Avary Holding (Shenzhen) Co., Limited. , HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. , GARUDA TECHNOLOGY CO., LTD.
Inventor： Yan-Lu Li , Mei Yang , Cheng-Jia Li
CPC classification number: H05K3/4644 , H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0011 , H05K3/0073 , H05K3/02 , H05K3/4038 , H05K2201/095
Abstract: A method of manufacture of a circuit board without annular through-hole rings and thus allowing a higher component density includes a base layer, a first wire pattern layer, and a second wire pattern layer on both sides of the base layer. A portion of the base layer not covered by the first wire pattern layer defines at least one first hole. The circuit board further includes a wire layer. The wire layer includes at least a first portion and a second portion connecting to the first portion. The first portion is filled in the first hole. The second portion is formed on the first portion extending away from the base layer. A diameter of the second portion is less than an aperture diameter of the first hole. The wire layer is electrically conductive between the first wire pattern layer and the second wire pattern layer through the first portion.
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公开(公告)号：US09764532B2
公开(公告)日：2017-09-19
申请号：US14838098
申请日：2015-08-27
Applicant: ISOLA USA CORP.
Inventor： Roland Schönholz
IPC: B32B15/08 , B32B27/04 , H05K1/02 , H05K1/11 , H05K3/46 , B32B5/02 , B32B5/26 , B32B15/14 , B32B15/20 , B32B37/00 , B32B37/02 , B32B37/26 , B32B37/06 , B32B38/10 , B32B37/14 , H05K1/14 , B32B37/30 , H05K3/42
CPC classification number: B32B15/08 , B32B5/024 , B32B5/26 , B32B15/14 , B32B15/20 , B32B37/0076 , B32B37/02 , B32B37/144 , B32B37/26 , B32B37/30 , B32B38/10 , B32B2260/023 , B32B2260/046 , B32B2262/101 , B32B2305/076 , B32B2305/72 , B32B2305/74 , B32B2305/77 , B32B2307/41 , B32B2307/412 , B32B2310/0831 , B32B2457/08 , H05K1/0278 , H05K1/028 , H05K1/118 , H05K1/147 , H05K3/429 , H05K3/4691 , H05K2201/0195 , H05K2201/09063 , H05K2201/09081 , H05K2201/095 , Y10T428/24314 , Y10T428/24322 , Y10T428/24331 , Y10T428/24612 , Y10T428/24802 , Y10T428/24851 , Y10T428/2486
Abstract: Prepregs having a UV curable resin layer located adjacent to a thermally curable resin layer wherein the UV curable resin layer includes at least one UV cured resin portion and at least one UV uncured resin as well as methods for preparing flexible printed circuit boards using the prepregs.
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Patent Agency Ranking
公开(公告)号：US20170202081A1
公开(公告)日：2017-07-13
申请号：US15391053
申请日：2016-12-27
Inventor： Takumi IKEDA , Masao KAINUMA , Yasuyuki KIMURA , Chang Hun GANG , Tae Uk GANG , Hyung Gon KIM
CPC classification number: H05K1/0274 , H01L31/02005 , H01L31/0203 , H01S5/02256 , H01S5/18 , H05K1/115 , H05K2201/095
Abstract: A package for an optical semiconductor device includes an eyelet, a signal lead inserted in a through hole formed in the eyelet, and sealing glass sealing the signal lead in the through hole. The signal lead includes a first portion, a second portion and a third portion that are greater in diameter than the first portion and on opposite sides of the first portion, a first tapered portion extending from the second portion to the first portion, and a second tapered portion extending from the third portion to the first portion. The first portion and the first and second tapered portions are buried in the sealing glass. The total length of a part of the second portion in the sealing glass and a part of the third portion in the sealing glass is 0.2 mm or less.
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公开(公告)号：US20170196084A1
公开(公告)日：2017-07-06
申请号：US15398778
申请日：2017-01-05
Applicant: IBIDEN CO., LTD.
Inventor： Teruyuki ISHIHARA
IPC: H05K1/11
CPC classification number: H05K1/115 , H05K1/11 , H05K1/112 , H05K1/116 , H05K1/14 , H05K3/0035 , H05K3/0038 , H05K3/429 , H05K2201/041 , H05K2201/095 , H05K2201/09509 , H05K2201/09518 , H05K2201/09827
Abstract: A printed wiring board includes a first insulating layer, a second conductor layer including first and second circuits, a second insulating layer covering the second conductor layer on the first insulating layer, a third conductor layer including first and second circuits, a third insulating layer covering the third conductor layer on the second insulating layer, a fourth conductor layer including first circuit, a second via conductor connecting the first circuits in the second and third conductor layers through the second insulating layer, and a first skip via conductor penetrating through the second circuit in the third conductor layer and connecting the second circuit in the second conductor layer and the first circuit in the fourth conductor layer through the second and third insulating layers. The second and third conductor layers are formed such that the second conductor layer has thickness t2 larger than thickness t3 of the third conductor layer.
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公开(公告)号：US20160278208A1
公开(公告)日：2016-09-22
申请号：US14834205
申请日：2015-08-24
Applicant: Multek Technologies Ltd.
Inventor： Kwan Pen , Pui Yin Yu
CPC classification number: H05K1/115 , H05K1/0216 , H05K1/0298 , H05K1/112 , H05K3/0058 , H05K3/06 , H05K3/181 , H05K3/188 , H05K3/42 , H05K3/422 , H05K3/424 , H05K3/429 , H05K3/4602 , H05K3/4623 , H05K3/4638 , H05K2201/095 , H05K2201/09545 , H05K2201/09554 , H05K2201/10303
Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.
Abstract translation: 用于制造电路板的选择性段通过电镀工艺选择性地将内部导电层互连在相同的通孔内的单独的段。 将电镀抗蚀剂施加到内芯的导电层，然后在无电镀处理之后剥离。 在电镀抗蚀剂上剥离化学镀导致通孔壁上的电镀不连续。 在随后的电镀工艺中，由于电镀不连续性，插头非导电层不能镀覆。 所得到的电路板结构在通孔内具有单独的电互连段。
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公开(公告)号：US20240313525A1
公开(公告)日：2024-09-19
申请号：US18198137
申请日：2023-05-16
Applicant: CABLE VISION ELECTRONICS CO., LTD.
Inventor： Chien-Chung LEE , Min-Chi TSENG , Cheng-Wei PENG , Yu-An CHEN
CPC classification number: H02H9/044 , H05K1/165 , H05K1/167 , H05K2201/095 , H05K2201/10666
Abstract: An electronic apparatus includes a printed circuit board, a terminal and a surge voltage protection structure. The printed circuit board includes a first plated through hole, a second plated through hole and a ground terminal. The surge voltage protection structure includes the first plated through hole and the second plated through hole. The first plated through hole is electrically connected to the terminal. The second plated through hole is connected to the ground terminal. A gap is defined between the first plated through hole and the second plated through hole. The first plated through hole receives a surge voltage to generate an electric arc across the gap and transmit the electric arc through the gap to the second plated through hole, so that the second plated through hole receives the electric arc to transfer an energy of the electric arc to the ground terminal.
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公开(公告)号：US20240304534A1
公开(公告)日：2024-09-12
申请号：US18594573
申请日：2024-03-04
Applicant: MEDIATEK INC.
Inventor： Shu-Wei HSIAO , Chung-Fa LEE
IPC: H01L23/498 , H01L23/00 , H05K1/11 , H05K3/46
CPC classification number: H01L23/49822 , H01L24/32 , H05K1/112 , H05K3/4644 , H01L2224/32225 , H01L2924/1207 , H05K2201/095
Abstract: A substrate structure and a package assembly with the substrate structure are provided. The substrate structure includes a first trace, a second trace, a first through-hole via (THV), a second THV formed in a build-up layer and a bridge trace. The first trace includes a first pad portion and a second pad portion separated from the first pad portion and arranged near a corner of the first pad portion. The first THV passes through the first pad portion and the second THV passes through the second pad portion. The first bridge trace formed in the substrate structure and thermally connected to the second THV and the first THV.
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