公开(公告)号：US08604357B2

公开(公告)日：2013-12-10

申请号：US12501044

申请日：2009-07-10

Applicant: Tsutomu Takeda

Inventor： Tsutomu Takeda

IPC: H05K3/42 ,  H05K3/30 ,  H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0237 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2203/0242 ,  H05K2203/175

Abstract: A wiring board has a plurality of wiring layers, a first land, a second land, a first via and a second via. The first land and the second land are formed on at least one wiring layer of the wiring board and are disposed to partially overlap with each other. The first via and the second via are formed in association with the first land and the second land, respectively. The first via and the second via electrically connect a first wiring layer and a second wiring layer of the plurality of wiring layers to each other. The wiring board has a separator that is formed by a hole that separates the first land and the second land from each other.

Abstract translation: 布线板具有多个布线层，第一片，第二片，第一片和第二片。 第一焊盘和第二焊盘形成在布线板的至少一个布线层上并且彼此部分地重叠。 第一通孔和第二通孔分别与第一焊盘和第二焊盘相关联地形成。 第一通孔和第二通孔将多个布线层中的第一布线层和第二布线层彼此电连接。 布线板具有由将第一焊盘和第二焊盘彼此分隔开的孔形成的隔板。

公开(公告)号：US20130319746A1

公开(公告)日：2013-12-05

申请号：US13960287

申请日：2013-08-06

Applicant: HARRIS CORPORATION

Inventor： ANDERS P. PEDERSEN ,  DANIEL A. ROBISON ,  ALAN W. MAST

IPC: H05K1/14

CPC classification number: H05K1/144 ,  H05K1/0219 ,  H05K1/111 ,  H05K1/117 ,  H05K1/142 ,  H05K3/301 ,  H05K3/366 ,  H05K3/403 ,  H05K2201/09145 ,  H05K2201/0919 ,  H05K2201/09481 ,  H05K2201/09809 ,  H05K2201/10446

Abstract: A method is for making a printed wiring board (PWB) assembly. The method may include forming a first PWB having a plurality of first electrically conductive pads, forming a second PWB including a plurality of electrically conductive traces having exposed ends on an edge surface of the second PWB, and covering the edge surface of the second PWB with an electrically conductive layer. The method may also include selectively removing portions of the electrically conductive layer to define a plurality of second electrically conductive pads electrically connected to corresponding ones of the exposed ends of the electrically conductive traces, and assembling the first and second PWBs together so that the first and second electrically conductive pads are electrically coupled together to define the PWB assembly.

公开(公告)号：US08592688B2

公开(公告)日：2013-11-26

申请号：US12649038

申请日：2009-12-29

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/16

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

公开(公告)号：US20130249112A1

公开(公告)日：2013-09-26

申请号：US13897202

申请日：2013-05-17

Applicant: Todd B. Myers ,  Nicolas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

Inventor： Todd B. Myers ,  Nicolas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US20130248234A1

公开(公告)日：2013-09-26

申请号：US13872650

申请日：2013-04-29

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/18

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：US08540523B2

公开(公告)日：2013-09-24

申请号：US12879951

申请日：2010-09-10

Applicant: Pascal Cornic ,  Jean-Philippe Coupez ,  Jérémie Hemery ,  Julien Boucher

Inventor： Pascal Cornic ,  Jean-Philippe Coupez ,  Jérémie Hemery ,  Julien Boucher

IPC: H01R12/00

CPC classification number: H05K1/0243 ,  H01P5/085 ,  H05K1/0219 ,  H05K1/025 ,  H05K1/0253 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/09809 ,  H05K2201/10189

Abstract: A connection device for high frequency signals is disclosed. The connection device includes a printed circuit having an external face and a transmission line printed on the external face, and a coaxial connector surface mounted on the external face of the printed circuit. The transmission line is connected to the connector by means of a bump contact belonging to the transmission line. A central core of the connector is connected to the bump contact. The printed circuit has at least one internal ground plane disposed parallel to the external face and contributing to the matching of the transmission line. The internal ground plane defines a perforation therethrough that faces the bump contact.

Abstract translation: 公开了一种用于高频信号的连接装置。 连接装置包括具有印刷在外表面上的外表面和传输线的印刷电路和安装在印刷电路的外表面上的同轴连接器表面。 传输线通过属于传输线的凸点接触连接到连接器。 连接器的中心芯连接到凸块接触。 印刷电路具有平行于外表面设置的至少一个内部接地平面，并有助于传输线的匹配。 内部接地平面限定穿过其穿过凸起接触的穿孔。

公开(公告)号：US08487446B2

公开(公告)日：2013-07-16

申请号：US13095317

申请日：2011-04-27

Applicant: Todd B Myers ,  Nicolas R Watts ,  Eric C Palmer ,  Jui Min Lim

Inventor： Todd B Myers ,  Nicolas R Watts ,  Eric C Palmer ,  Jui Min Lim

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US08471649B2

公开(公告)日：2013-06-25

申请号：US12376738

申请日：2007-09-07

Applicant: Jeff Devereux ,  Fritz Gerd Berger ,  William A. Johnston ,  Mohammad Ali Tassoudji ,  Scott Aldern

Inventor： Jeff Devereux ,  Fritz Gerd Berger ,  William A. Johnston ,  Mohammad Ali Tassoudji ,  Scott Aldern

IPC: H01P3/08 ,  H01P5/12

CPC classification number: H01P5/085 ,  H05K1/0243 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09718 ,  H05K2201/09809 ,  Y10T29/49139

Abstract: A compact Ku band microwave diplexer configured as a three port surface mount component on a miniature alumina substrate. Input signals occurring at a common port having frequencies within a first pass band are passed to a second port while being isolated from signals occurring at a third port. Signals occurring at the third port are passed to the common port while being isolated from the signals at the second port. A microstrip dual spur line filter is used combined with open circuit stubs to provide enhanced second harmonic suppression on the transmit side, while using a coupled line microstrip filter on the receive side. This approach allows for compact size and automated component assembly through pick and place and reflow manufacturing techniques.

Abstract translation: 在微型氧化铝基板上构造为三端口表面安装部件的紧凑型Ku波段微波双工器。 在具有第一通带内的频率的公共端口处发生的输入信号被传递到第二端口，同时与在第三端口处发生的信号隔离。 在第三个端口发生的信号被传递到公共端口，同时与第二个端口的信号隔​​离。 微带双支路线路滤波器与开路短路结合使用，以在接收侧使用耦合线路微带滤波器，在发射侧提供增强的二次谐波抑制。 这种方法允许通过拾取和放置和回流制​​造技术实现紧凑的尺寸和自动部件组装。

公开(公告)号：US20130105212A1

公开(公告)日：2013-05-02

申请号：US13667080

申请日：2012-11-02

Applicant: Japan Electronic Materials Corp.

Inventor： Mitsuaki Tsuboi

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K1/115 ,  G01R3/00 ,  G01R31/2889 ,  H05K1/0251 ,  H05K3/4046 ,  H05K3/4061 ,  H05K3/4629 ,  H05K2201/097 ,  H05K2201/09809 ,  Y10T29/49126

Abstract: A multilayer insulating substrate with excellent electrical characteristics and a method for manufacturing the multilayer insulating substrate. A multilayer insulating substrate is composed of a first insulating layer including first central conductor regions to constitute through electrodes and first outer conductor regions surrounding the first central conductor regions, and a second insulating layer including second central conductor regions to constitute through electrodes and second outer conductor regions surrounding the second central conductor regions, wherein the second insulating layer is laminated on the first insulating layer to allow electrical connection between the first central conductor regions and the second central conductor regions and electrical connection between the first outer conductor regions and the second outer conductor regions so that a coaxial wiring structure is configured by the first outer conductor regions and the second outer conductor regions relative to the first central conductor regions and the second central conductor regions.

Abstract translation: 具有优异电气特性的多层绝缘基板和制造多层绝缘基板的方法。 多层绝缘基板由包括构成贯通电极的第一中心导体区域和围绕第一中心导体区域的第一外部导体区域构成的第一绝缘层，以及包含第二中心导体区域的第二绝缘层构成通孔电极和第二外部导体 围绕所述第二中心导体区域的区域，其中所述第二绝缘层层压在所述第一绝缘层上，以允许所述第一中心导体区域和所述第二中心导体区域之间的电连接以及所述第一外导体区域与所述第二外导体之间的电连接 使得相对于第一中心导体区域和第二中心导体区域，由第一外部导体区域和第二外部导体区域构成同轴布线结构。

公开(公告)号：US20130048344A1

公开(公告)日：2013-02-28

申请号：US13220825

申请日：2011-08-30

Applicant: CHOON LEONG LOU

Inventor： CHOON LEONG LOU

IPC: H05K1/11

CPC classification number: H05K1/0237 ,  H05K3/103 ,  H05K2201/09027 ,  H05K2201/09036 ,  H05K2201/09809 ,  H05K2201/10356

Abstract: In one embodiment of the present invention, a high frequency circuit board includes a laminate having a top surface with a groove; a semi-rigid cable positioned in the groove of the laminate; and a passivation layer filling the groove; wherein the semi-rigid cable is configured to transmit a high frequency signal, and the semi-rigid cable comprises a central conductor, an outer conductor, and an insulating layer between the central conductor and the outer conductor.

Abstract translation: 在本发明的一个实施例中，高频电路板包括具有凹槽的顶表面的叠层; 位于层压板的槽中的半刚性电缆; 以及填充所述凹槽的钝化层; 其中所述半刚性电缆被配置为传输高频信号，并且所述半刚性电缆包括在所述中心导体和所述外导体之间的中心导体，外导体和绝缘层。