公开(公告)号：US06967153B2

公开(公告)日：2005-11-22

申请号：US10248688

申请日：2003-02-10

Applicant: Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

Inventor： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC: H01L21/60 ,  H05K3/34 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3484 ,  H05K2201/09863 ,  H05K2203/043 ,  H05K2203/0568 ,  H05K2203/0594

Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at least with an opening that exposes the pre-formed bump. Solder material is deposited into the openings and then a reflow process is conducted fusing the solder material and the pre-formed bump together to form a spherical bump. The pre-formed bump and the solder material may be fabricated using different constituents.

Abstract translation: 提供了一种用于在其上具有多个接合焊盘的晶片上形成凸块的凸块制造工艺。 具有暴露各个接合焊盘的多个开口的图案化焊接掩模层形成在晶片上。 通过底部的横截面积中的开口面积以及通过开口的顶部的开口面积比通过中间部分的横截面积的开口面积小， 部分开幕。 将焊料沉积到开口中，然后进行回流工艺，将焊料材料熔合在一起，以在开口内形成球形凸块。 最后，去除焊接掩模层。 此外，在晶片上形成图案化的焊料掩模层之前，至少具有暴露预形成的凸块的开口之前，可以在晶片的焊盘上形成预形成的凸块。 将焊料沉积到开口中，然后进行回流工艺，将焊料材料和预形成的凸块熔合在一起形成球形凸块。 可以使用不同的成分制造预形成的凸块和焊料材料。

公开(公告)号：US20040066633A1

公开(公告)日：2004-04-08

申请号：US10662368

申请日：2003-09-16

Inventor： Yoshitarou Yazaki ,  Tomohiro Yokochi ,  Koji Kondo ,  Toshikazu Harada ,  Yoshihiko Shiraishi

IPC: H05K001/00 ,  H05K001/18 ,  H05K007/02 ,  H05K007/06 ,  H05K007/08

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Conductive paste containing tin particles and silver particles is packed in a substantially cylindrical via hole formed in a thermoplastic resin film that interposes between conductor patterns and is hot-pressed from both sides. When the metal particles contained in the conductive paste are sintered to form a unified conductive compound, the volume of the conductive paste shrinks. Synchronously, the resin film around the via-hole protrudes into the via-hole. Therefore, the shape of the side wall on the cross-section of the conductive compound provides an arch shape, and a side wall adjacent to a junction part of the conductive compound, which contacts the conductor pattern, is formed with an inclination. Therefore, it is possible to prevent the stress concentration due to deformation of the board.

Abstract translation: 含有锡颗粒和银颗粒的导电糊料被包装在形成在热塑性树脂膜中的大致圆柱形的通孔中，该热塑性树脂膜介于导体图案之间并且从两侧被热压。 当包含在导电浆料中的金属颗粒被烧结以形成统一的导电化合物时，导电浆料的体积收缩。 同时，通孔周围的树脂膜突出到通孔中。 因此，导电性化合物的横截面上的侧壁的形状形成拱形，并且与导体图案接触的导电性化合物的接合部分相邻的侧壁形成倾斜。 因此，可以防止由于板的变形引起的应力集中。

公开(公告)号：US06713687B2

公开(公告)日：2004-03-30

申请号：US10022222

申请日：2001-12-20

Applicant: Yoshitarou Yazaki ,  Tomohiro Yokochi ,  Koji Kondo ,  Toshikazu Harada ,  Yoshihiko Shiraishi

Inventor： Yoshitarou Yazaki ,  Tomohiro Yokochi ,  Koji Kondo ,  Toshikazu Harada ,  Yoshihiko Shiraishi

IPC: H05K111

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Conductive paste containing tin particles and silver particles is packed in a substantially cylindrical via hole formed in a thermoplastic resin film that interposes between conductor patterns and is hot-pressed from both sides. When the metal particles contained in the conductive paste are sintered to form a unified conductive compound, the volume of the conductive paste shrinks. Synchronously, the resin film around the via-hole protrudes into the via-hole. Therefore, the shape of the side wall on the cross-section of the conductive compound provides an arch shape, and a side wall adjacent to a junction part of the conductive compound, which contacts the conductor pattern, is formed with an inclination. Therefore, it is possible to prevent the stress concentration due to deformation of the board.

Abstract translation: 含有锡颗粒和银颗粒的导电糊料被包装在形成在热塑性树脂膜中的大致圆柱形的通孔中，该热塑性树脂膜介于导体图案之间并且从两侧被热压。 当包含在导电浆料中的金属颗粒被烧结以形成统一的导电化合物时，导电浆料的体积收缩。 同时，通孔周围的树脂膜突出到通孔中。 因此，导电性化合物的横截面上的侧壁的形状形成拱形，并且与导体图案接触的导电性化合物的接合部分相邻的侧壁形成倾斜。 因此，可以防止由于板的变形引起的应力集中。

公开(公告)号：US06641898B2

公开(公告)日：2003-11-04

申请号：US10024470

申请日：2001-12-21

Applicant: Yoshitaro Yazaki ,  Yoshihiko Shiraishi ,  Koji Kondo ,  Toshikazu Harada ,  Tomohiro Yokochi

Inventor： Yoshitaro Yazaki ,  Yoshihiko Shiraishi ,  Koji Kondo ,  Toshikazu Harada ,  Tomohiro Yokochi

IPC: B32B300

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T428/24917

Abstract: A heated and pressed printed wiring board is made by filling via holes formed in layers of insulating film of the wiring board with an interlayer conducting material. The insulating film is stacked with conductor patterns, and each conductor pattern closes a via hole. The interlayer conducting material forms a solid conducting material in the via holes after a heating a pressing procedure. The solid conducting material includes two types of conducting materials. The first type of conducting material includes a metal, and the second type of conductive material includes an alloy formed by the metal and conductor metal of the conductor patterns. The conductor patterns are electrically connected reliably without relying on mere mechanical contact.

公开(公告)号：US20020079135A1

公开(公告)日：2002-06-27

申请号：US10022222

申请日：2001-12-20

Inventor： Yoshitarou Yazaki ,  Tomohiro Yokochi ,  Koji Kondo ,  Toshikazu Harada ,  Yoshihiko Shiraishi

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Conductive paste containing tin particles and silver particles is packed in a substantially cylindrical via hole formed in a thermoplastic resin film that interposes between conductor patterns and is hot-pressed from both sides. When the metal particles contained in the conductive paste are sintered to form a unified conductive compound, the volume of the conductive paste shrinks. Synchronously, the resin film around the via-hole protrudes into the via-hole. Therefore, the shape of the side wall on the cross-section of the conductive compound provides an arch shape, and a side wall adjacent to a junction part of the conductive compound, which contacts the conductor pattern, is formed with an inclination. Therefore, it is possible to prevent the stress concentration due to deformation of the board.

Abstract translation: 含有锡颗粒和银颗粒的导电糊料被包装在形成在热塑性树脂膜中的大致圆柱形的通孔中，该热塑性树脂膜介于导体图案之间并且从两侧被热压。 当包含在导电浆料中的金属颗粒被烧结以形成统一的导电化合物时，导电浆料的体积收缩。 同时，通孔周围的树脂膜突出到通孔中。 因此，导电性化合物的横截面上的侧壁的形状形成拱形，并且与导体图案接触的导电性化合物的接合部分相邻的侧壁形成倾斜。 因此，可以防止由于板的变形引起的应力集中。

公开(公告)号：US5746927A

公开(公告)日：1998-05-05

申请号：US762882

申请日：1996-12-12

Applicant: Kaoru Hashimoto ,  Tatuo Chiyonobu ,  Kyoichiro Kawano ,  Koji Watanabe ,  Masato Wakamura ,  Joe Yamaguchi

Inventor： Kaoru Hashimoto ,  Tatuo Chiyonobu ,  Kyoichiro Kawano ,  Koji Watanabe ,  Masato Wakamura ,  Joe Yamaguchi

IPC: H01L23/498 ,  H05K3/34 ,  B44C1/22

CPC classification number: H05K3/3452 ,  H01L23/49811 ,  H01L23/49866 ,  H05K3/3463 ,  H01L2224/16225 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/3025 ,  H05K2201/0373 ,  H05K2201/09863 ,  H05K2201/10984 ,  H05K2203/0594 ,  H05K2203/1105

Abstract: An electrical connecting device including a first circuit board providing thereon with input/output terminals, each of the terminals having a tip surface coated with gallium and a second circuit board providing thereon with contact terminals, each of the terminals having a tip surface coated with indium or tin. A low-melting point alloy layer is formed by a mutual action between gallium and indium or tin, when the input/output terminals of the first circuit board are in contact with the respective terminals of the second circuit board and the terminals are electrically connected to each other. The second metal layer includes a plurality of wire-like metal supports extending substantially perpendicular to the surface of the terminal and a low-melting point metal retained by the wire-like metal supports.

Abstract translation: 一种电连接装置，包括在其上设置有输入/输出端子的第一电路板，每个端子具有涂覆有镓的尖端表面和在其上设置有接触端子的第二电路板，每个端子具有涂覆有铟的尖端表面 或锡。 当第一电路板的输入/输出端子与第二电路板的各个端子接触时，通过镓和铟或锡之间的相互作用形成低熔点合金层，并且端子电连接到 彼此。 第二金属层包括大致垂直于端子表面延伸的多个线状金属支撑体和由线状金属支撑体保持的低熔点金属。

公开(公告)号：US5610371A

公开(公告)日：1997-03-11

申请号：US403678

申请日：1995-03-14

Applicant: Kaoru Hashimoto ,  Tatuo Chiyonobu ,  Kyoichiro Kawano ,  Koji Watanabe ,  Masato Wakamura ,  Joe Yamaguchi

Inventor： Kaoru Hashimoto ,  Tatuo Chiyonobu ,  Kyoichiro Kawano ,  Koji Watanabe ,  Masato Wakamura ,  Joe Yamaguchi

IPC: H01L23/498 ,  H05K3/34 ,  H05K1/18

CPC classification number: H05K3/3452 ,  H01L23/49811 ,  H01L23/49866 ,  H05K3/3463 ,  H01L2224/16225 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/3025 ,  H05K2201/0373 ,  H05K2201/09863 ,  H05K2201/10984 ,  H05K2203/0594 ,  H05K2203/1105

Abstract: An electrical connecting device including a first circuit board providing thereon with input/output terminals, each of the terminals having a tip surface coated with gallium and a second circuit board providing thereon with contact terminals, each of the terminals having a tip surface coated with indium or tin. A low-melting point alloy layer is formed by a mutual action between gallium and indium or tin, when the input/output terminals of the first circuit board are in contact with the respective terminals of the second circuit board and the terminals are electrically connected to each other. The second metal layer includes a plurality of wire-like metal supports extending substantially perpendicular to the surface of the terminal and a low-melting point metal retained by the wire-like metal supports.

Abstract translation: 一种电连接装置，包括在其上设置有输入/输出端子的第一电路板，每个端子具有涂覆有镓的尖端表面和在其上设置有接触端子的第二电路板，每个端子具有涂覆有铟的尖端表面 或锡。 当第一电路板的输入/输出端子与第二电路板的各个端子接触时，通过镓和铟或锡之间的相互作用形成低熔点合金层，并且端子电连接到 彼此。 第二金属层包括大致垂直于端子表面延伸的多个线状金属支撑体和由线状金属支撑体保持的低熔点金属。

公开(公告)号：US4510347A

公开(公告)日：1985-04-09

申请号：US447159

申请日：1982-12-06

Applicant: Raymond E. Wiech, Jr.

Inventor： Raymond E. Wiech, Jr.

IPC: H05K1/03 ,  H05K1/09 ,  H05K3/04 ,  H05K3/06 ,  H05K3/07 ,  H05K3/10 ,  H05K3/12 ,  H05K1/02

CPC classification number: H05K3/1258 ,  H05K3/045 ,  H05K3/07 ,  H05K3/107 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09118 ,  H05K2201/098 ,  H05K2201/09863 ,  H05K2201/2072 ,  H05K2203/0353 ,  H05K3/06 ,  H05K3/108

Abstract: A method of forming electrically conductive paths within grooves formed in a substrate wherein the width of the grooves is of the same order of magnitude as the thickness of an electrically conductive layer deposited on the substrate and in the grooves. The substrate with grooves therein is exposed to a medium whereby electrically conductive material from the medium deposits substantially uniformly on all surfaces of the substrate which are exposed to the medium. In this way, the build-up of conductive material in grooves will take place along the side walls as well as the bottom of the grooves. If the layer is of substantially the same order of magnitude as the width of the groove (about one half the groove width or greater), the grooves will fill up with conductive material. The remainder of the substrate will ultimately provide a substantially flat conductive layer on the substrate surface. The conductive material is then removed by an action which removes exposed conductor along the entire substrate surface at a uniform rate whereby the conductor will be substantially entirely removed from the substrate except for the portion thereof within the grooves. In this way an electrically conductive path of predetermined geometry is provided.

公开(公告)号：US09913381B2

公开(公告)日：2018-03-06

申请号：US14460587

申请日：2014-08-15

Applicant: Point Engineering Co., Ltd.

Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Kyoung Ja Yun

IPC: H05K1/18 ,  H05K3/00 ,  H05K7/00 ,  H01L33/48 ,  H01L33/62

CPC classification number: H05K3/0052 ,  H01L33/48 ,  H01L33/62 ,  H01L2924/0002 ,  H05K1/183 ,  H05K2201/09718 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/10 ,  H05K2201/10106 ,  H05K2201/10121 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A base substrate which prevents burrs generated during the cutting process includes: multiple conductive layers stacked in one direction with respect to the base substrate; at least one insulation layer being alternately stacked with said conductive layers and electrically separating said conductive layers; and a through-hole penetrating said base substrate covering said insulation layer at the contact region where said cut surface and said insulation layer meet during the cutting of said base substrate in accordance with a predetermined region of the chip substrate. A method of manufacturing the base substrate includes alternately stacking conductive layers and insulation layers and forming a through-hole.

公开(公告)号：US09603248B2

公开(公告)日：2017-03-21

申请号：US13779944

申请日：2013-02-28

Applicant: IBIDEN CO., LTD.

Inventor： Teruyoshi Hisada ,  Takashi Nakane

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0554

Abstract: A wiring board includes a board including a core, a conductive layer on the core, and a laminated structure over the core and conductive layer, and a stacked structure formed in the board and including a through-hole conductor through the core and a via conductor in the laminated structure. The through-hole conductor has though-hole portion through the core and land portion on the core, the laminated structure includes an insulation layer in which the via conductor is formed, the via conductor is stacked on the land portion such that the stacked structure including the through-hole and via conductors is formed through the core and the insulation layer, and the stacked structure is formed such that the through-hole portion has end connected to the land portion and the end has width set greater than width of bottom of the via conductor and smaller than width of top of the via conductor.