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    MOVABLE HEATSINK UTILIZING FLEXIBLE HEAT PIPES
    31.
    发明申请
    MOVABLE HEATSINK UTILIZING FLEXIBLE HEAT PIPES 审中-公开

    公开(公告)号：US20190045663A1

    公开(公告)日：2019-02-07

    申请号：US16017731

    申请日：2018-06-25

    Applicant: Intel Corporation

    Inventor： David Shia ,  Evan Chenelly ,  Mohanraj Prabhugoud

    IPC: H05K7/20 ,  F28D15/02 ,  G06F1/20 ,  H05K1/18 ,  H05K1/02

    Abstract: Embodiments described herein may include apparatuses, systems and/or processes to provide a cooling apparatus that includes a first heatsink, a second movable heatsink and a flexible thermal conductor physically and thermally coupled with the first and second heatsinks, where the flexible thermal conductor is to flex and remain thermally coupled with the first heatsink and the second heatsink, when the second heatsink is moved relative to the first heatsink. The first heatsink may be coupled to a heat source such as a processor that may be coupled with a PCB. Also, the movable heatsink may allow access to components, such as dual in-line memory modules (DIMMs) that are next to the first heatsink and under the movable second heatsink. Other embodiments may be described and/or claimed.

    CONVERGED TEST PLATFORMS AND PROCESSES FOR CLASS AND SYSTEM TESTING OF INTEGRATED CIRCUITS
    32.
    发明申请
    CONVERGED TEST PLATFORMS AND PROCESSES FOR CLASS AND SYSTEM TESTING OF INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20180252772A1

    公开(公告)日：2018-09-06

    申请号：US15447095

    申请日：2017-03-01

    Applicant: Intel Corporation

    Inventor： Abram M. Detofsky ,  Evan M. Fledell ,  Mustapha A. Abdulai ,  John M. Peterson ,  Dinia P. Kitendaugh ,  Pooya Tadayon ,  Jin Pan ,  David Shia

    IPC: G01R31/3185 ,  G01R31/28

    CPC classification number: G01R31/31908 ,  G01R31/2886 ,  G01R31/31905

    Abstract: A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.

    Micro positioning test socket and methods for active precision alignment and co-planarity feedback
    34.
    发明授权
    Micro positioning test socket and methods for active precision alignment and co-planarity feedback 有权
    微定位测试插座和主动精密对准和共平面反馈的方法

    公开(公告)号：US09255945B2

    公开(公告)日：2016-02-09

    申请号：US14202291

    申请日：2014-03-10

    Applicant: Intel Corporation

    Inventor： Abram M. Detofsky ,  Todd P. Albertson ,  David Shia

    IPC: G01R31/00 ,  G01R1/04 ,  G01B7/31 ,  G01R1/067 ,  G01R31/28 ,  H05K1/02

    CPC classification number: G01R1/0408 ,  G01B7/31 ,  G01R1/0483 ,  G01R1/06794 ,  G01R31/2891 ,  H05K1/0268 ,  H05K2203/162 ,  H05K2203/166

    Abstract: Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.

    Abstract translation: 描述了用于测试微电子封装结构/器件的方法和结构。 这些方法可以包括将设备放置在浮动载体中，其中浮动载体通过设置在插座壳体的四个角落中的销钉联接到插座壳体，并且其中至少两个致动马达设置在插座壳体内，并且微型 通过利用电容耦合或光纤对准系统来调节装置，其中设置在插座壳体中的对准结构和设置在装置内的对准封装球之间的最大测量电容或最大测量强度表示装置的最佳对准。 方法还包括通过使用电容耦合技术进行有源共平面检测的方法。

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