公开(公告)号：US09236348B2

公开(公告)日：2016-01-12

申请号：US14188093

申请日：2014-02-24

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Scott Smith ,  Elizabeth Ann Burke

IPC: H01L23/12 ,  H01L21/00 ,  H05K1/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H05K1/18 ,  H01L23/522 ,  H01L23/48 ,  H01L21/48 ,  H05K3/46 ,  H01L25/10 ,  H01L21/60

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L2021/60 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/144 ,  H05K1/185 ,  H05K1/189 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/467 ,  H05K3/4673 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/09136 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method of forming a buried die module includes providing an initial laminate flex layer and forming a die opening through the initial laminate flex layer. A first uncut laminate flex layer is secured to the first surface of the initial laminate flex layer by way of an adhesive material and a die is positioned within the die opening of the initial laminate flex layer and onto the adhesive material. A second uncut laminate flex layer is secured to the second surface of the initial laminate flex layer by way of an adhesive material and the adhesive materials are then cured. Vias and metal interconnects are formed in and on the first and second uncut laminate flex layers, with each of the metal interconnects extending through a respective via and being directly metalized to a metal interconnect on the initial laminate flex layer or a die pad on the die.

Abstract translation: 形成掩埋模具模块的方法包括提供初始层叠柔性层并通过初始层压柔性层形成模具开口。 第一未切割层压柔性层通过粘合剂材料固定到初始层压柔性层的第一表面，并且模具定位在初始层压柔性层的模具开口内并粘附到粘合剂材料上。 第二未切割层压柔性层通过粘合剂材料固定到初始层压柔性层的第二表面上，然后固化粘合剂材料。 在第一和第二未切割的层叠柔性层中和第二未切割的层叠柔性层上形成通孔和金属互连，其中每个金属互连件延伸通过相应的通孔，并且直接金属化到初始层压柔性层上的金属互连或模具上的管芯焊盘 。

公开(公告)号：US20150373829A1

公开(公告)日：2015-12-24

申请号：US14649204

申请日：2014-01-14

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Akihiro Ishikawa ,  Toru Yamamoto ,  Kazuya Inokuchi

IPC: H05K1/02

CPC classification number: H05K1/028 ,  H05K1/024 ,  H05K1/025 ,  H05K1/0278 ,  H05K1/0281 ,  H05K3/0044 ,  H05K3/282 ,  H05K3/4652 ,  H05K3/4691 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2203/0207 ,  H05K2203/0228

Abstract: A printed wiring board includes: an inner layer structure body containing at least an inner layer insulative base material composed of a glass cloth and resin which covers the glass cloth and not containing a resin insulative base material composed only of resin; outer layer wiring formed on a first face of the inner layer structure body; and a solder resist layer formed on a surface of the outer layer wiring, wherein in the inner layer structure body, an opening part is formed, and the solder resist layer is composed of a first ink part covering at least the outer layer wiring that is formed on a partial region of the first face which corresponds to the opening part and a second ink part interposing both ends of the first ink part and being lower in flexibility than the first ink part.

Abstract translation: 印刷电路板包括：内层结构体，至少包含由玻璃布构成的内层绝缘基材和覆盖玻璃布的树脂，不含仅由树脂构成的树脂绝缘基材; 形成在所述内层结构体的第一面上的外层布线; 以及形成在所述外层布线的表面上的阻焊层，其中在所述内层结构体中形成有开口部，所述阻焊层由至少覆盖外层布线的第一墨部构成， 形成在与开口部相对应的第一面的部分区域上，以及插入第一墨部的两端并且柔性比第一墨部低的第二墨部。

公开(公告)号：US09167702B2

公开(公告)日：2015-10-20

申请号：US13626477

申请日：2012-09-25

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Kenji Suzuki

IPC: H05K3/30 ,  H05K1/18 ,  H05K3/46 ,  H05K3/00 ,  H05K1/02

CPC classification number: H05K3/306 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/1531 ,  H05K1/0218 ,  H05K1/0222 ,  H05K1/185 ,  H05K3/0094 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09981 ,  H05K2201/10712 ,  H05K2203/1394 ,  Y10T29/49133 ,  Y10T29/49135 ,  H01L2924/00

Abstract: A method of manufacturing a component-built-in wiring substrate which exhibits excellent reliability, through improvement of adhesion between a resin filler and a core substrate, is provided. In some embodiments the method comprises a core substrate preparation step for preparing a core substrate, an accommodation-hole forming step for forming an accommodation hole in the core substrate, and a through-hole forming step for forming through-holes. In a plating-layer forming step, a plating layer is formed on an inner wall surface of the accommodation hole and plating layers are formed on the inner wall surfaces of the through-holes, which become through-hole conductors each having a hollow. In an accommodation step, a component is accommodated in the accommodation hole. In a resin charging step, a resin filler is filled into a gap between component side-surfaces and the inner wall surface of the accommodation hole and into the hollows.

Abstract translation: 提供了通过提高树脂填充剂和芯基板之间的粘附性而制造具有优异可靠性的组件内置布线基板的方法。 在一些实施例中，该方法包括用于制备芯基板的芯基板准备步骤，用于在芯基板中形成收纳孔的容纳孔形成步骤和用于形成通孔的通孔形成步骤。 在电镀层形成工序中，在容纳孔的内壁面上形成镀层，在形成有中空部的通孔导体的贯通孔的内壁面上形成镀覆层。 在调节步骤中，部件容纳在容纳孔中。 在树脂填充工序中，将树脂填料填充到部件侧面与容纳孔的内壁面之间的间隙中，并填充到中空部内。

公开(公告)号：US09159693B2

公开(公告)日：2015-10-13

申请号：US14063699

申请日：2013-10-25

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jin Won Choi

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H05K3/46 ,  H05K1/18 ,  H05K3/00

CPC classification number: H01L24/80 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/12042 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0097 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/09727 ,  H05K2203/061 ,  H05K2203/063 ,  H05K2203/1536 ,  H01L2924/00

Abstract: Provided is a hybrid substrate with high density and low density substrate areas and a method of manufacturing the same. The hybrid substrate with high density and low density substrate areas includes a low density substrate layer having a cavity and a low density area, a high density substrate layer mounted in the cavity of the low density substrate layer and formed of a high density area having a higher pattern density than that of the low density area, an insulating support layer comprising a deposition area formed on upper portions, lower portions and the upper and lower portions of the high density substrate layer and the low density substrate layer, insulating layer vias passing through the deposition area of the insulating support layer and connected to patterns of the high density substrate layer and the low density substrate layer, and an outer pattern layer.

Abstract translation: 提供了具有高密度和低密度基板区域的混合基板及其制造方法。 具有高密度和低密度衬底区域的混合衬底包括具有空腔和低密度面积的低密度衬底层，安装在低密度衬底层的空腔中的高密度衬底层，并由具有 具有比低密度区域更高的图案密度的绝缘支撑层，包括形成在高密度衬底层的上部，下部和上部和下部的沉积区域和低密度衬底层的绝缘支撑层，绝缘层通孔 绝缘支撑层的沉积区域和与高密度衬底层和低密度衬底层的图案相连，以及外部图案层。

公开(公告)号：US20150243609A1

公开(公告)日：2015-08-27

申请号：US14190745

申请日：2014-02-26

Applicant: International Business Machines Corporation

Inventor： Mark C. Lamorey ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

IPC: H01L23/64 ,  H01L23/367 ,  H01L23/498 ,  H01L23/36 ,  H01L23/552 ,  H01L23/50

CPC classification number: H01L23/552 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/17181 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H02J7/0042 ,  H02J7/0052 ,  H02J7/345 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/144 ,  H05K1/162 ,  H05K2201/0116 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/0999 ,  H05K2201/10515 ,  H05K2201/1056 ,  H01L2924/014 ,  H01L2924/00

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract translation: 封装组件包括管芯堆叠和相关使用方法。 包装组件包括具有第一表面，第二表面和与从第一表面延伸到第二表面的通孔邻接的第三表面的基底。 组件还包括管芯叠层，导电层和盖。 芯片堆叠包括位于衬底中的通孔内的芯片。 导电层的一部分设置在基板的第三表面上。 盖的一部分设置在第一芯片和导电层的部分之间。 导电层被配置为与电力耦合，并且盖被配置为与地耦合。 盖的部分可以用作电容器的第一板，并且导电层的部分可以用作电容器的第二板。

公开(公告)号：US20150201488A1

公开(公告)日：2015-07-16

申请号：US14585657

申请日：2014-12-30

Applicant: Kabushiki Kaisha Toshiba

Inventor： Nobuto MANAGAKI ,  Tadahiro SASAKI ,  Atsuko IIDA ,  Yutaka ONOZUKA ,  Hiroshi YAMADA

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0222 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0187 ,  H05K2201/0195

Abstract: A wiring board of an embodiment includes a through via, a first insulating film disposed around the through via, a second insulating film disposed around the first insulating film, a third insulating film disposed around the second insulating film and a resin disposed around the third insulating film. The resin includes fillers. The second insulating film has a relative permittivity lower than a relative permittivity of the first insulating film. The third insulating film has a relative permittivity higher than a relative permittivity of the second insulating film.

Abstract translation: 实施方式的布线基板包括通孔，设置在贯通通孔周围的第一绝缘膜，设置在第一绝缘膜周围的第二绝缘膜，设置在第二绝缘膜周围的第三绝缘膜，以及设置在第三绝缘膜周围的树脂 电影。 树脂包括填料。 第二绝缘膜的相对介电常数低于第一绝缘膜的相对介电常数。 第三绝缘膜的相对介电常数高于第二绝缘膜的相对介电常数。

公开(公告)号：US09084353B2

公开(公告)日：2015-07-14

申请号：US13807325

申请日：2011-06-28

Applicant: Jan De Geest ,  Stefaan Hendrik Jozef Sercu

Inventor： Jan De Geest ,  Stefaan Hendrik Jozef Sercu

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189

Abstract: A circuit board (1) is provided comprising a plurality of insulating layers, at least one ground layer and at least one layer comprising signal traces. The circuit board comprises at least a first conductive via (17) and a second conductive via (17). The first conductive via and the second conductive via penetrate through at least a first insulating layer of the plurality of insulating layers and are connected to a signal trace. The first conductive via and the second conductive via are arranged adjacent each other. At least in the first insulating layer the first conductive via and the second conductive via are separated in a first direction of separation (R) by a first adjustment portion comprising a dielectric material property different from the first insulating layer.

Abstract translation: 提供电路板（1），其包括多个绝缘层，至少一个接地层和至少一个包含信号迹线的层。 电路板包括至少第一导电通孔（17）和第二导电通孔（17）。 第一导电通孔和第二导电通孔穿透多个绝缘层中的至少第一绝缘层，并连接到信号迹线。 第一导电通孔和第二导电通孔彼此相邻布置。 至少在第一绝缘层中，通过包括不同于第一绝缘层的介电材料性质的第一调节部分，第一导电通孔和第二导电通孔在第一分离方向（R）分离。

公开(公告)号：US09078370B2

公开(公告)日：2015-07-07

申请号：US13589560

申请日：2012-08-20

Applicant: Yuichi Sugiyama ,  Tatsuro Sawatari ,  Yusuke Inoue ,  Masashi Miyazaki ,  Yoshiki Hamada ,  Toshiyuki Kagawa

Inventor： Yuichi Sugiyama ,  Tatsuro Sawatari ,  Yusuke Inoue ,  Masashi Miyazaki ,  Yoshiki Hamada ,  Toshiyuki Kagawa

IPC: H05K1/16 ,  H05K1/18 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/16 ,  H01L24/19 ,  H01L2224/04105 ,  H05K1/0271 ,  H05K1/185 ,  H05K3/4697 ,  H05K2201/0187

Abstract: Provided is a substrate with a built-in electronic component that can minimize an occurrence of a deformation such as warping or distortion of the substrate with a built-in electronic component, which is caused by a difference in rigidity between a region of low rigidity and a region of high rigidity that are formed in a core layer thereof. In the substrate with a built-in electronic component, electronic components 12 are respectively housed in a plurality of housing portions 11a1 that are formed in a core layer 11a, and in the core layer 11a, a plurality of openings 11a2 filled with an insulator 11k are formed.

Abstract translation: 本发明提供一种具有内置电子部件的基板，其能够通过内置电子部件来最小化诸如翘曲或变形的变形的发生，所述变形是由于低刚性区域之间的刚性差和 形成在其芯层中的高刚性区域。 在具有内置电子部件的基板中，电子部件12分别容纳在形成在芯层11a中的多个收容部11a1中，在芯层11a中，填充有绝缘体11k的多个开口部11a2 形成。

公开(公告)号：US20150181722A1

公开(公告)日：2015-06-25

申请号：US14637655

申请日：2015-03-04

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Kenji SUZUKI

IPC: H05K3/30 ,  H05K3/00

CPC classification number: H05K3/306 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/1531 ,  H05K1/0218 ,  H05K1/0222 ,  H05K1/185 ,  H05K3/0094 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09981 ,  H05K2201/10712 ,  H05K2203/1394 ,  Y10T29/49133 ,  Y10T29/49135 ,  H01L2924/00

Abstract: A method of manufacturing a component-built-in wiring substrate which exhibits excellent reliability, through improvement of adhesion between a resin filler and a core substrate, is provided. In some embodiments the method comprises a core substrate preparation step for preparing a core substrate, an accommodation-hole forming step for forming an accommodation hole in the core substrate, and a through-hole forming step for forming through-holes. In a plating-layer forming step, a plating layer is formed on an inner wall surface of the accommodation hole and plating layers are formed on the inner wall surfaces of the through-holes, which become through-hole conductors each having a hollow. In an accommodation step, a component is accommodated in the accommodation hole. In a resin charging step, a resin filler is filled into a gap between component side-surfaces and the inner wall surface of the accommodation hole and into the hollows.

Abstract translation: 提供了通过提高树脂填充剂和芯基板之间的粘附性而制造具有优异可靠性的组件内置布线基板的方法。 在一些实施例中，该方法包括用于制备芯基板的芯基板准备步骤，用于在芯基板中形成收纳孔的容纳孔形成步骤和用于形成通孔的通孔形成步骤。 在电镀层形成工序中，在容纳孔的内壁面上形成镀层，在形成有中空部的通孔导体的贯通孔的内壁面上形成镀覆层。 在调节步骤中，部件容纳在容纳孔中。 在树脂填充工序中，将树脂填料填充到部件侧面与容纳孔的内壁面之间的间隙中，并填充到中空部内。

公开(公告)号：US09066424B2

公开(公告)日：2015-06-23

申请号：US13941554

申请日：2013-07-15

Applicant: Hong Kong Applied Science and Technology Research Institute Company Limited

Inventor： Dan Yang ,  Song He ,  Yuxing Ren ,  Xunqing Shi

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/00 ,  C23C28/00

CPC classification number: H05K1/024 ,  C23C28/40 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0224 ,  H05K1/0231 ,  H05K1/165 ,  H05K1/185 ,  H05K3/0058 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/068 ,  H05K2201/0723 ,  H05K2201/09136 ,  H05K2201/09536 ,  H05K2201/09981 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10098 ,  Y10T156/1057

Abstract: The presently claimed invention is to provide a package for compact RF signal system, and a method to form the package thereof in order to miniaturize the size of package, improve signal integrity, and reduce manufacturing cost. The package comprises a hybrid substrate with a sandwiched structure, in which the hybrid substrate comprises an upper layer and a lower layer with different dielectric properties being separated by an interposer for improving electrical isolation and mechanical stiffness. Metal layers are formed on the sidewalls of the opening to surround an active component, such that the metal sidewalls together with two ground plates in the upper and lower layers constitute a self-shielding enclosure inside the package to protect the active component.

Abstract translation: 目前要求保护的发明是提供一种用于紧凑型RF信号系统的封装，以及形成其封装的方法，以便使封装尺寸小型化，提高信号完整性并降低制造成本。 该封装包括具有夹层结构的混合基板，其中混合基板包括上层，并且具有不同介电特性的下层由用于改善电隔离和机械刚度的插入件分离。 金属层形成在开口的侧壁上以包围有源部件，使得金属侧壁与上层和下层中的两个接地板一起构成封装内的自屏蔽外壳，以保护有源部件。