公开(公告)号：US06998540B2

公开(公告)日：2006-02-14

申请号：US10426326

申请日：2003-04-29

Applicant: Robert Edward Belke, Jr. ,  Vivek A. Jairazbhoy ,  Thomas B. Krautheim ,  William F. Quitty, Jr.

Inventor： Robert Edward Belke, Jr. ,  Vivek A. Jairazbhoy ,  Thomas B. Krautheim ,  William F. Quitty, Jr.

IPC: H01R12/04

CPC classification number: H05K3/44 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2201/09745 ,  H05K2201/0979 ,  H05K2201/09854 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49156

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics.

公开(公告)号：US06658731B1

公开(公告)日：2003-12-09

申请号：US09703554

申请日：2000-11-01

Applicant: Lakhi Nandlal Goenka ,  Mohan R. Paruchuri ,  Thomas B Krautheim

Inventor： Lakhi Nandlal Goenka ,  Mohan R. Paruchuri ,  Thomas B Krautheim

IPC: H05K302

CPC classification number: H05K3/4007 ,  H05K3/062 ,  H05K3/363 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/209 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/1184 ,  Y10S439/943 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155

Abstract: In conventional ETM circuit structures a pin connector in which the pin is etched from the ETM substrate and the mating cavity is etched from the ETM substrate to be mated. The connector utilizes the subtractive ETM structure processing to define any one of several pin-cavity configurations. The pin serves as an anchor with the metallurgical bonds with solder in the cavity that forms on the copper surfaces of the ETM circuit structure to give good mechanical strength to the connection. In particular four different configurations of interconnections are shown and described.

Abstract translation: 在传统的ETM电路结构中，一个引脚连接器，其中从ETM基板蚀刻引脚，并且从ETM基板蚀刻配合腔以进行配合。 连接器利用减法ETM结构处理来定义几个引脚腔配置中的任何一个。 该引脚用作锚固件，其中在空腔中与焊料的冶金结合形成在ETM电路结构的铜表面上，以为连接提供良好的机械强度。 特别地示出和描述了四种不同的互连配置。

公开(公告)号：US20030133277A1

公开(公告)日：2003-07-17

申请号：US10168403

申请日：2002-11-27

Inventor： Kinji Saijo ,  Kazuo Yoshida ,  Hiroaki Okamoto ,  Shinji Ohsawa

IPC: H01R009/00

CPC classification number: H05K1/0221 ,  H05K3/062 ,  H05K3/4647 ,  H05K2201/0361 ,  H05K2201/09254 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A structure of a multilayer printed wiring board having a wiring lead-out port can be easily formed. A large number of products can be easily manufactured with good size reproducibility. A method of manufacturing the same is also are disclosed. The multilayer printed wiring board is characterized by having a signal circuit conductor perfectly covered by an earth circuit in its inside and a wiring lead-out port. A signal circuit conductor having a branch pattern is preferable. The multilayer printed wiring board is manufactured by selectively etching the copper of a cladding sheet manufactured by bonding a copper foil to a nickel foil with 0.1-3% reduction and forming a signal circuit conductor perfectly covered by an earth circuit and the wiring lead-out port.

Abstract translation: 可以容易地形成具有布线引出口的多层印刷线路板的结构。 可以容易地制造大量的产品，具有良好的尺寸再现性。 还公开了一种制造该方法的方法。 多层印刷电路板的特征在于具有完全被其内部的接地电路覆盖的信号电路导体和布线引出端口。 具有分支图案的信号电路导体是优选的。 多层印刷线路板是通过选择性地蚀刻通过将铜箔结合到镍箔上而制造的包覆片的铜而制造的，所述镍箔具有0.1-3％的还原，并形成完全被接地电路覆盖的信号电路导体和布线引出 港口。

公开(公告)号：US06568073B1

公开(公告)日：2003-05-27

申请号：US09036494

申请日：1998-03-06

Applicant: Naoki Fukutomi ,  Hidehiro Nakamura ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Masanori Nakamura ,  Kouichi Kaitou ,  Atsushi Kuwano ,  Itsuo Watanabe ,  Masahiko Itabashi

Inventor： Naoki Fukutomi ,  Hidehiro Nakamura ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Masanori Nakamura ,  Kouichi Kaitou ,  Atsushi Kuwano ,  Itsuo Watanabe ,  Masahiko Itabashi

IPC: H05K310

CPC classification number: H05K3/4658 ,  G01R1/07314 ,  H05K3/062 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/428 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10S29/016 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158

Abstract: The present invention provides a process for the fabrication of a wiring board, which comprises the following steps: (a) forming a first wiring pattern on a first side of a self-supporting carrier metal foil so as to obtain a self-supporting wiring sheet comprising the carrier metal foil and the first wiring pattern; (b) superposing and pressing the first side of said self-supporting wiring sheet on and against an insulating substrate so that the first wiring pattern is_embedded in the insulating substrate and constitutes a surface with the insulating substrate; and (c) etching off desired portions of said carrier metal foil to form a second wiring pattern made of said carrier metal foil remaining on the surface constituted by the insulating substrate and the first wiring pattern. The present invention also provides the wiring board for electrical tests so fabricated.

Abstract translation: 本发明提供一种制造布线板的方法，其包括以下步骤：（a）在自支撑载体金属箔的第一面上形成第一布线图案，以获得自支撑布线板 包括载体金属箔和第一布线图案; （b）将所述自支撑布线板的第一侧叠置并压在绝缘基板上，使得第一布线图案嵌入在绝缘基板中并与绝缘基板构成表面; 和（c）蚀刻所述载体金属箔的期望部分，以形成由保留在由绝缘基板和第一布线图案构成的表面上的所述载体金属箔制成的第二布线图案。 本发明还提供了如此制造的用于电测试的接线板。

公开(公告)号：US06501031B1

公开(公告)日：2002-12-31

申请号：US09655809

申请日：2000-09-06

Applicant: Andrew Z. Glovatsky ,  Jay D. Baker ,  Robert Edward Belke ,  Myron Lemecha ,  Richard Keith McMillan ,  Thomas B. Krautheim

Inventor： Andrew Z. Glovatsky ,  Jay D. Baker ,  Robert Edward Belke ,  Myron Lemecha ,  Richard Keith McMillan ,  Thomas B. Krautheim

IPC: H05K111

CPC classification number: H05K3/445 ,  H05K3/386 ,  H05K3/4038 ,  H05K3/4092 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2201/09581 ,  H05K2203/1438 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49172

Abstract: A multi-layer electronic circuit board design 10 having a core member 12, a pair of dielectric layers 14, 16 disposed thereon, and a first circuit portion 20 which is coupled to the dielectric layer 14 and core member 12 using a layer of adhesive material 18. Circuit board design 10 further having selectively formed “blind” apertures, vias or cavities 22 formed through the first circuit portion 20, dielectric layer 14, and adhesive layer 18, thereby exposing core member 12.

Abstract translation: 具有芯构件12，设置在其上的一对电介质层14,16的多层电子电路板设计10以及使用粘合材料层连接到电介质层14和芯构件12的第一电路部分20 电路板设计10还具有选择性地形成通过第一电路部分20形成的“盲”孔，通孔或空腔22，电介质层14和粘合层18，从而露出芯构件12。

公开(公告)号：US20020137347A1

公开(公告)日：2002-09-26

申请号：US09815226

申请日：2001-03-22

Inventor： Bharat Z. Patel ,  Jay D. Baker ,  Lakhi N. Goenka ,  Michael Allen Howey ,  Mohan R. Paruchuri ,  Richard Keith McMillan

IPC: H01L021/311

CPC classification number: H05K3/44 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0361 ,  H05K2201/0397 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/0733 ,  H05K2203/1184

Abstract: A method 10 for making a multi-layer circuit board 70 having at least one electrically conductive interconnection portion or nullvianull 72 which extends within the board 70 and at least one air-bridge 74. The method 10 includes the steps of forming protuberances 13 upon a core member 12, attaching pre-circuit assemblies 32, 34 to the core member 12, thereby forming the circuit board 70 while concomitantly and selectively extending at least one of the protuberances 13 within the formed circuit board 70.

Abstract translation: 制造多层电路板70的方法10具有至少一个在板70内和至少一个空气桥74上延伸的导电互连部分或“通孔”72。方法10包括以下步骤：形成突起13 在芯构件12上，将预电路组件32,34附接到芯构件12，从而形成电路板70，同时并且选择性地延伸形成的电路板70内的至少一个突起13。

公开(公告)号：US20020136873A1

公开(公告)日：2002-09-26

申请号：US09812449

申请日：2001-03-20

Inventor： Delin Li ,  Richard Keith McMillan

IPC: H05K001/11 ,  B32B003/00 ,  H05K003/10 ,  B32B015/00

CPC classification number: H05K3/429 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method 10, 110 for making multi-layer circuit boards having metallized apertures 38, 40, 130, 132 which may be selectively and electrically grounded and having at least one formed air-bridge 92, 178.

Abstract translation: 一种用于制造具有金属化孔38,40,130,132的多层电路板的方法10,110，其可以选择性地和电接地并且具有至少一个形成的空气桥92,178。

公开(公告)号：US20020086243A1

公开(公告)日：2002-07-04

申请号：US09203148

申请日：1998-12-01

Inventor： DELIN LI ,  ACHYUTA ACHARI ,  ALICE DAWN ZITZMANN ,  ROBERT EDWARD BELKE JR. ,  BRENDA JOYCE NATION ,  EDWARD MCLESKEY ,  MOHAN R. PARUCHURI ,  LAKHI NANDLAL GOENKA

IPC: B44C001/22 ,  C23F001/02

CPC classification number: H05K3/062 ,  H05K3/205 ,  H05K3/386 ,  H05K3/4685 ,  H05K2201/0361 ,  H05K2201/0394 ,  H05K2203/0369 ,  H05K2203/0376

Abstract: A multilayer circuit board having air bridge crossover structures and an additive method for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit.

Abstract translation: 一种具有空气桥交叉结构的多层电路板及其制造方法，其特征在于，该电路包括专门设计的金属强化层，用于机械地和/或电气地加固电路。

公开(公告)号：US06412168B1

公开(公告)日：2002-07-02

申请号：US09655750

申请日：2000-09-06

Applicant: Andrew Z. Glovatsky ,  Jay D. Baker

Inventor： Andrew Z. Glovatsky ,  Jay D. Baker

IPC: H01K310

CPC classification number: H05K3/4038 ,  H05K3/386 ,  H05K3/44 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0397 ,  H05K2201/09554 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26.

Abstract translation: 具有选择性地形成的孔或腔26的多层电子电路板设计10

公开(公告)号：US5738797A

公开(公告)日：1998-04-14

申请号：US649377

申请日：1996-05-17

Applicant: Robert E. Belke, Jr. ,  Michael G. Todd ,  Andrew Z. Glovatsky ,  Alice D. Zitzmann

Inventor： Robert E. Belke, Jr. ,  Michael G. Todd ,  Andrew Z. Glovatsky ,  Alice D. Zitzmann

IPC: C23F1/02 ,  H05K3/00 ,  H05K3/06 ,  H05K3/20 ,  H05K3/46 ,  B44C1/22 ,  C23F1/00

CPC classification number: H05K3/4685 ,  C23F1/02 ,  H05K3/062 ,  H05K3/205 ,  H05K2201/0361 ,  H05K2201/0394 ,  H05K2201/09018 ,  H05K2201/09118 ,  H05K2203/0152 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K3/0014

Abstract: A three dimensional multi-layer circuit structure is formed by partially etching a foil having a coating. A pre-circuit is formed by providing a metal foil, applying a photodefinable photoresist to each side of the metal foil, selectively exposing and developing the photoresist leaving exposed areas and unexposed areas and, plating the unexposed areas with a second metal. The pre-circuit is placed in an etching solution and removed after the etching solution partially etches the metal foil to undercut the second metal. The partially etched pre-circuit is then bent into a predetermined shape. The partially etched pre-circuit is then inserted into a mold cavity so that at least one surface of the circuit structure is adjacent to the mold. The mold is filled with a polymer resin so that the polymer resin encapsulates at least a portion of the partially etched pre-circuit and substantially fills the undercut. The molded circuit structure is then removed from the mold and the metallic foil is further etched to complete the forming of the circuit.

Abstract translation: 通过部分蚀刻具有涂层的箔形成三维多层电路结构。 通过提供金属箔，在金属箔的每一侧上施加可光限定的光致抗蚀剂，选择性地暴露和显影光致抗蚀剂以形成暴露区域和未曝光区域，以及用第二金属镀覆未曝光区域来形成预制电路。 将预电路放置在蚀刻溶液中，并且在蚀刻溶液部分蚀刻金属箔以切割第二金属之后移除。 然后将部分蚀刻的预循环弯曲成预定的形状。 然后将部分蚀刻的预制电路插入模腔中，使得电路结构的至少一个表面与模具相邻。 模具填充有聚合物树脂，使得聚合物树脂封装部分蚀刻的预循环的至少一部分并且基本上填充底切。 然后将模制电路结构从模具中取出，并且金属箔被进一步蚀刻以完成电路的形成。