公开(公告)号：US20150060914A1

公开(公告)日：2015-03-05

申请号：US14251534

申请日：2014-04-11

Applicant: LEXTAR ELECTRONICS CORPORATION

Inventor： Yei-How Ho

IPC: H01L33/58 ,  H01L33/60 ,  H01L33/00

CPC classification number: F21V7/22 ,  F21V5/04 ,  F21V7/041 ,  F21V7/045 ,  F21Y2115/10 ,  H01L33/0095 ,  H01L33/58 ,  H01L33/60 ,  H05K1/0274 ,  H05K2201/09909 ,  H05K2201/10106 ,  H05K2201/2054

Abstract: A light-emitting assembly and a method for manufacturing the same are provided. The light-emitting assembly includes a circuit board with a light-emitting element and a plurality of optical microstructures disposed thereon. The optical microstructures adjacent to the light-emitting element absorb or guide a portion of light emitted from the light-emitting element.

Abstract translation: 提供发光组件及其制造方法。 发光组件包括具有发光元件的电路板和设置在其上的多个光学微结构。 与发光元件相邻的光学微结构吸收或引导从发光元件发射的光的一部分。

公开(公告)号：US08952518B2

公开(公告)日：2015-02-10

申请号：US14006527

申请日：2012-07-20

Applicant: Mahiro Tsujino ,  Manabu Miyahara

Inventor： Mahiro Tsujino ,  Manabu Miyahara

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/057 ,  H01L23/10

CPC classification number: H01L24/42 ,  H01L23/057 ,  H01L23/10 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/171 ,  H05K3/3442 ,  H05K2201/09172 ,  H05K2201/09181 ,  H05K2201/09409 ,  H05K2201/09909 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device housing package includes a base body having, on its upper surface, a mounting region of a semiconductor device; a frame body having a frame-like portion disposed on the upper surface of the base body, surrounding the mounting region, and an opening penetrating through from an inner side of the frame-like portion to an outer side thereof; a flat plate-like insulating member disposed in the opening, extending from an interior of the frame body to an exterior thereof; wiring conductors disposed on an upper surface of the insulating member, extending from the interior of the frame body to the exterior thereof; and a metallic film disposed on a part of the upper surface of the insulating member, the metallic film lying outside the frame body surrounding the wiring conductors.

Abstract translation: 半导体器件壳体封装包括：基体，其上表面具有半导体器件的安装区域; 框架体，其具有设置在基体的上表面上的框状部分，围绕安装区域，以及从框状部分的内侧穿过其外侧的开口; 设置在所述开口中的平板状绝缘构件，从所述框体的内部延伸到其外部; 布线导体设置在绝缘构件的上表面上，从框体的内部延伸到其外部; 以及设置在所述绝缘构件的上表面的一部分上的金属膜，所述金属膜位于围绕所述布线导体的框架体的外侧。

公开(公告)号：US20150016107A1

公开(公告)日：2015-01-15

申请号：US14378581

申请日：2013-02-07

Applicant: TRIDONIC JENNERSDORF GMBH

Inventor： Florian Wimmer ,  Peter Pachler ,  Norbert Reitinger ,  Juergen Gumhold

IPC: H01L33/60 ,  F21K99/00 ,  H01L25/075 ,  H01L25/13 ,  H01L33/64 ,  H01L33/52

CPC classification number: H01L33/60 ,  H01L24/48 ,  H01L25/0753 ,  H01L25/13 ,  H01L33/52 ,  H01L33/64 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/181 ,  H05K1/021 ,  H05K1/0274 ,  H05K2201/09909 ,  H05K2201/10106 ,  H05K2201/2054 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An LED module, including a carrier having high reflectivity, wherein a metal layer, preferably a silver layer or a layer of high-purity aluminum, is applied to the carrier. Also disclosed is an LED module, including a carrier having high reflectivity, wherein a metal layer is applied to the carrier, at least one LED chip, and a dam, wherein the metal layer partially covers the surface of the carrier lying under the dam.

Abstract translation: 一种LED模块，包括具有高反射率的载体，其中将金属层，优选银层或高纯度铝层施加到载体上。 还公开了一种LED模块，其包括具有高反射率的载体，其中将金属层施加到载体，至少一个LED芯片和坝，其中金属层部分地覆盖位于坝下面的载体的表面。

公开(公告)号：US20150011100A1

公开(公告)日：2015-01-08

申请号：US14060873

申请日：2013-10-23

Applicant: GERMANE SYSTEMS, LC

Inventor： MICHAEL STOCK ,  SCOTT SEMMLER

IPC: H01R12/70 ,  H01R43/18

CPC classification number: H01R13/533 ,  H01R12/7029 ,  H05K1/141 ,  H05K3/00 ,  H05K3/366 ,  H05K7/1405 ,  H05K2201/09045 ,  H05K2201/09909 ,  H05K2201/10159 ,  H05K2201/10325 ,  H05K2201/10606 ,  Y10T29/49117 ,  Y10T156/1089

Abstract: A circuit board that is to be mounted in a connector socket includes a plurality of electrical connectors located along a side edge of the circuit board. Retention bosses are formed on first and second opposite sides of the circuit board, each of the retention bosses protruding from a surface of the circuit board and extending parallel to and adjacent to the first edge of the circuit board. When the first edge of the circuit board is inserted into a slot of a connector socket, contact surfaces of the first and second retention bosses contact top surfaces of the connector socket to help immobilize the circuit board with respect to the connector socket. Adhesive layers on the contact surfaces of the first and second retention bosses may adhere to the top surfaces of the connector socket to help hold the circuit board immobile with respect to the connector socket.

Abstract translation: 要安装在连接器插座中的电路板包括沿着电路板的侧边缘定位的多个电连接器。 保持凸起形成在电路板的第一和第二相对侧上，每个保持凸起从电路板的表面突出并且平行于并邻近电路板的第一边缘延伸。 当电路板的第一边缘插入到连接器插座的插槽中时，第一和第二保持凸台的接触表面接触连接器插座的顶部表面，以帮助电路板相对于连接器插座固定。 第一和第二保持凸起的接触表面上的粘合层可以粘附到连接器插座的顶表面，以帮助保持电路板相对于连接器插座不动。

公开(公告)号：US20140290988A1

公开(公告)日：2014-10-02

申请号：US13850315

申请日：2013-03-26

Applicant: Todd Mathew Spath

Inventor： Todd Mathew Spath

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H05K1/09 ,  H05K3/02 ,  H05K2201/0108 ,  H05K2201/0329 ,  H05K2201/0391 ,  H05K2201/09909 ,  H05K2203/1142 ,  Y10T29/49162

Abstract: A patterned conductive structure includes a transparent substrate having a substrate surface. A conductive polymer layer is formed on the substrate surface. The conductive polymer layer has electrically conductive areas and deactivated areas that are less electrically conductive than the conductive areas. The conductive areas and the deactivated areas form a conductive pattern in the polymer layer. One or more transparent dielectric patches that are less electrically conductive than the deactivated areas are formed over at least a portion of one or more deactivated areas and one or more conductive wires are formed over at least one of the dielectric patches.

Abstract translation: 图案化导电结构包括具有基板表面的透明基板。 在基板表面上形成导电聚合物层。 导电聚合物层具有比导电区域导电性更差的导电区域和去活化区域。 导电区域和去活化区域在聚合物层中形成导电图案。 在一个或多个去活化区域的至少一部分上形成一个或多个比非去活化区域更不导电的透明电介质贴片，并且在至少一个电介质贴片上形成一个或多个导线。

公开(公告)号：US08741766B2

公开(公告)日：2014-06-03

申请号：US13905845

申请日：2013-05-30

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/48

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有集成凸块焊盘的迹线的衬底。 在芯片凸块焊盘或集成凸块焊盘之间间隙地形成焊接掩模贴片。 焊接掩模贴片包含不可润湿的材料。 导电凸块材料沉积在集成的凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得导电凸块材料设置在管芯凸块焊盘和集成凸块焊盘之间。 凸块材料在集成的凸块焊盘周围没有焊接掩模的情况下回流以形成半导体管芯和衬底之间的互连。 焊接掩模贴片将导电凸块材料限制在回流焊中芯片凸块焊盘或集成凸块焊盘的占位面积内。 互连可以具有不可熔的基底和易熔盖。

公开(公告)号：US08659172B2

公开(公告)日：2014-02-25

申请号：US12963919

申请日：2010-12-09

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76885 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/10145 ,  H01L2224/10175 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81208 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有具有多个具有互连部位的多个导体迹线的多个管芯凸块焊盘和衬底的半导体管芯。 在芯片凸块焊盘或互连部位之间间隙地形成焊接掩模贴片。 导电凸块材料沉积在互连部位或模具凸块上。 将半导体管芯安装到衬底上，使得导电凸块材料设置在管芯凸块焊盘和互连部位之间。 导电凸块材料在管芯凸块焊盘或互连部位周围没有焊接掩模回流，以在半导体管芯和衬底之间形成互连结构。 焊接掩模贴片将导电凸块材料限制在管芯凸块焊盘或互连部位内。 互连结构可以包括可熔部分和不可熔部分。 密封剂沉积在半导体管芯和衬底之间。

公开(公告)号：US20130264704A1

公开(公告)日：2013-10-10

申请号：US13905845

申请日：2013-05-30

Applicant: Stats ChipPAC, Ltd

Inventor： Rajendra D. Pendse

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有集成凸块焊盘的迹线的衬底。 在芯片凸块焊盘或集成凸块焊盘之间间隙地形成焊接掩模贴片。 焊接掩模贴片包含不可润湿的材料。 导电凸块材料沉积在集成的凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得导电凸块材料设置在管芯凸块焊盘和集成凸块焊盘之间。 凸块材料在集成的凸块焊盘周围没有焊接掩模的情况下回流以形成半导体管芯和衬底之间的互连。 焊接掩模贴片将导电凸块材料限制在回流焊中芯片凸块焊盘或集成凸块焊盘的占位面积内。 互连可以具有不可熔的基底和易熔盖。

公开(公告)号：US08499998B2

公开(公告)日：2013-08-06

申请号：US12576572

申请日：2009-10-09

Applicant: Yoshiyuki Wada ,  Tadahiko Sakai

Inventor： Yoshiyuki Wada ,  Tadahiko Sakai

IPC: B23K31/02 ,  H01L21/70

CPC classification number: H05K3/3442 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/186 ,  H05K3/305 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09909 ,  H05K2201/10636 ,  H05K2201/10977 ,  Y02P70/611 ,  Y02P70/613

Abstract: A core layer has on its front surface a pair of connecting electrodes forming a wiring pattern and a resist formed between the pair of electrodes; an electronic component having a pair of connecting terminals; a solder part joining between electrodes and connecting terminals; and a sealing resin part filling a gap between the bottom surface of the electronic component and the front surface of the core layer and covering the resist and the solder part, to prevent a defect of a component built-in printed circuit substrate.

Abstract translation: 核心层在其前表面上形成一对形成布线图案的连接电极和形成在该对电极之间的抗蚀剂; 具有一对连接端子的电子部件; 连接电极和连接端子之间的焊料部分; 以及密封树脂部分，填充电子部件的底表面和芯层的前表面之间的间隙并覆盖抗蚀剂和焊料部分，以防止组件内置印刷电路基板的缺陷。

公开(公告)号：US08476761B2

公开(公告)日：2013-07-02

申请号：US13476899

申请日：2012-05-21

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L23/48

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有集成凸块焊盘的迹线的衬底。 在芯片凸块焊盘或集成凸块焊盘之间间隙地形成焊接掩模贴片。 焊接掩模贴片包含不可润湿的材料。 导电凸块材料沉积在集成的凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得导电凸块材料设置在管芯凸块焊盘和集成凸块焊盘之间。 凸块材料在集成的凸块焊盘周围没有焊接掩模的情况下回流以形成半导体管芯和衬底之间的互连。 焊接掩模贴片将导电凸块材料限制在回流焊中芯片凸块焊盘或集成凸块焊盘的占位面积内。 互连可以具有不可熔的基底和易熔盖。