公开(公告)号：US20230199951A1

公开(公告)日：2023-06-22

申请号：US17742916

申请日：2022-05-12

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jin Uk LEE ,  Chi Won HWANG ,  Eun Sun KIM

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/111 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/10159

Abstract: A printed circuit board includes: a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; and a bridge embedded in the wiring substrate and having a plurality of connection pads thereon. An uppermost wiring layer of the plurality of wiring layers includes a plurality of bump pads connected to the plurality of connection pads, and a pitch between at least two adjacent connection pads of the plurality of connection pads is larger than a pitch between at least two adjacent ones of the plurality of bump pads.

公开(公告)号：US11683883B2

公开(公告)日：2023-06-20

申请号：US17184666

申请日：2021-02-25

Applicant: SEIKO EPSON CORPORATION

Inventor： Yukio Okamura ,  Toru Matsuyama

IPC: H05K1/02 ,  H05K1/18 ,  H01L23/498 ,  G01R31/3185 ,  H05K1/11

CPC classification number: H05K1/029 ,  G01R31/318538 ,  G01R31/318572 ,  G01R31/318597 ,  H01L23/49816 ,  H05K1/0268 ,  H05K1/0287 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10212

Abstract: There is provided a semiconductor apparatus including a memory controller; a CPU; a high-speed communication controller; a memory operation terminal group that includes a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller; a high-speed communication terminal group that includes a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller; an inspection terminal group that includes a plurality of inspection terminals for acquiring information from the CPU and performing debugging; and a terminal mounting surface at which the memory operation terminal group, the high-speed communication terminal group, and the inspection terminal group are provided, in which at the terminal mounting surface, a first inspection terminal among the plurality of inspection terminals is located between the memory operation terminal group and the high-speed communication terminal group.

公开(公告)号：US11678437B2

公开(公告)日：2023-06-13

申请号：US17210907

申请日：2021-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyun Seok ,  Gyu Chae Lee ,  Jeong Hyeon Cho

IPC: H05K1/18 ,  H01L25/18 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L25/18 ,  H05K1/117 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal receive the first signal from the buffer at the same time. The first connection terminal be is closer to the buffer as compared with the second connection terminal. The third connection terminal is closer to the buffer as compared with the fourth connection terminal.

公开(公告)号：US20190237152A1

公开(公告)日：2019-08-01

申请号：US16124379

申请日：2018-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-ho Lee ,  Sung-joo Park ,  Young Yun ,  Yong-jin Kim ,  Jae-jun Lee

IPC: G11C29/38 ,  G11C29/36 ,  G11C11/409

CPC classification number: G11C29/38 ,  G01K7/01 ,  G11C11/409 ,  G11C29/36 ,  H05K1/117 ,  H05K1/181 ,  H05K2201/10151 ,  H05K2201/10159 ,  H05K2201/10522

Abstract: A memory device including: a loopback circuit for performing a loopback operation, wherein the loopback operation comprises receiving, via a loopback channel, test signals provided from a test device and feeding back the test signals to the test device via the loopback channel; and an information management circuit for outputting information of the memory device to the loopback channel.

公开(公告)号：US20190191561A1

公开(公告)日：2019-06-20

申请号：US16208353

申请日：2018-12-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: H05K1/11 ,  G06F13/40 ,  H05K1/18 ,  G11C7/10 ,  G11C5/06 ,  G11C5/04 ,  G06F1/18 ,  G11C11/4093 ,  G06F13/16 ,  G11C11/408 ,  G06F15/78

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

公开(公告)号：US20190116660A1

公开(公告)日：2019-04-18

申请号：US16218344

申请日：2018-12-12

Applicant: INTEL CORPORATION

Inventor： Andrew MORNING-SMITH ,  Eugene LIM ,  Meng ZHAI

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/028 ,  H05K1/0278 ,  H05K1/189 ,  H05K3/4691 ,  H05K2201/055 ,  H05K2201/10159

Abstract: Embodiments include devices and method related to a foldable printed circuit board that may be used in SSD applications. One embodiment relates to a foldable printed circuit board comprising a first rigid portion, a second rigid portion, and a first flexible region coupling the first rigid portion to the second rigid portion. The foldable printed circuit board also includes a third rigid portion and a second flexible region coupling the second rigid portion to the third rigid portion, wherein the first rigid portion and the third rigid portion each have a width that is less than that of the second rigid portion. Other embodiments are described and claimed.

公开(公告)号：US20180343768A1

公开(公告)日：2018-11-29

申请号：US15696273

申请日：2017-09-06

Applicant: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD. ,  HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： YI-LIN YANG ,  CHUNG-JEN HUNG ,  CHING-JOU CHEN

IPC: H05K7/20 ,  H01L23/467

CPC classification number: H05K7/20145 ,  H01L23/467 ,  H05K1/181 ,  H05K2201/10159

Abstract: A heat dissipating system includes a wind tunnel, a first electronic element, and a second electronic element. The wind tunnel defines a top air inlet channel and a separated bottom, and a top air discharging channel and a separated bottom air discharging channel. Air entering the bottom air inlet channel dissipates heat produced by the first electronic element to the top air discharging channel, to flow out of the wind tunnel. Air entering the top air inlet channel flows to the bottom air discharging channel to dissipate heat produced by the second electronic element, this arrangement avoids heated air from one element being exhausted onto another element.

公开(公告)号：US20180213645A1

公开(公告)日：2018-07-26

申请号：US15928874

申请日：2018-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Gaynes ,  Jeffrey D. Gelorme ,  Robert P. Kuder, II ,  Daniel J. Littrell ,  Thomas E. Lombardi ,  Marie-Claude Paquet ,  Frank L. Pompeo ,  David L. Questad ,  James Speidell ,  Sri M. Sri-Jayantha ,  Son K. Tran

IPC: H05K1/18 ,  H05K3/30 ,  H01R4/02

CPC classification number: H05K1/18 ,  H01R4/02 ,  H01R12/51 ,  H01R12/7041 ,  H01R43/205 ,  H05K1/0271 ,  H05K1/181 ,  H05K3/30 ,  H05K3/305 ,  H05K3/366 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10106 ,  H05K2201/10159 ,  H05K2201/10166 ,  H05K2201/10977

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

公开(公告)号：US10020028B2

公开(公告)日：2018-07-10

申请号：US15351600

申请日：2016-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F17/50 ,  G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  G11C5/02 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US20180174941A1

公开(公告)日：2018-06-21

申请号：US15678197

申请日：2017-08-16

Applicant: JONG-PIL SON

Inventor： JONG-PIL SON

IPC: H01L23/36 ,  H01L25/18 ,  H01L27/118 ,  H01L27/108 ,  H01L23/535 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L23/373 ,  H01L21/4882 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49568 ,  H01L23/535 ,  H01L23/538 ,  H01L24/06 ,  H01L24/09 ,  H01L24/14 ,  H01L24/17 ,  H01L24/18 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/10805 ,  H01L27/118 ,  H01L2023/4037 ,  H01L2023/4043 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2023/4068 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H05K1/181 ,  H05K2201/10159 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor memory device includes an integrated circuit (IC) chip structure, wherein the IC chip includes a substrate, a memory cell disposed on the substrate, and a local well disposed on the substrate, wherein a conductivity type of the local well is different from a conductivity type of the substrate, a wiring stack structure disposed on the IC chip structure, wherein the wiring stack structure includes a signal transfer pattern connected to the memory cell through a signal interconnector, and a thermal dispersion pattern connected to the local well through a thermal interconnector, and a heat transfer structure connected to the thermal dispersion pattern for transferring heat to the thermal dispersion pattern from a heat source.