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    Semiconductor structure
    41.
    发明授权
    Semiconductor structure 有权
    半导体结构

    公开(公告)号：US08981536B1

    公开(公告)日：2015-03-17

    申请号：US14048078

    申请日：2013-10-08

    Applicant: Chipbond Technology Corporation

    Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

    IPC: H01L29/06 ,  H01L23/58 ,  H01L23/495 ,  H01L23/00 ,  H01L29/02

    CPC classification number: H01L23/562 ,  H01L23/31 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.

    Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 第二保护层揭示第一抗应力区，并包括第二表面，第一横向侧，第二横向侧和第一连接侧。 第二表面包括第二抗应力区。 第一侧面的延伸线与第二侧面的延伸线相交形成第一交点。 通过连接第一交点和第一连接侧的两个点形成的区域是第一抗应力区域。 第三保护层显示第二抗应力区域，并且包括突出在第一表面上的第二连接侧，以形成平行于第一连接侧的突出线。

    SEMICONDUCTOR STRUCTURE
    42.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权
    半导体结构

    公开(公告)号：US20150069584A1

    公开(公告)日：2015-03-12

    申请号：US14042976

    申请日：2013-10-01

    Applicant: Chipbond Technology Corporation

    Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

    IPC: H01L23/00

    CPC classification number: H01L23/562 ,  H01L23/28 ,  H01L23/3192 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.

    Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 来自第一底部边缘的第一延伸线与第二延伸线从第二底部边缘相交以形成第一基点。 第一投影线形成在第一表面上，第一投影线的延长线与第二底边缘相交形成第一交点，第二投影线形成在第一表面上，第二投影线形成在第二表面的延伸线上 投影线与第一底边相交形成第二交点。 通过连接第一基点，第一交点和第二交点的区域是第一抗应力区域。

    BUMPING PROCESS AND STRUCTURE THEREOF
    46.
    发明申请
    BUMPING PROCESS AND STRUCTURE THEREOF 有权
    保鲜工艺及其结构

    公开(公告)号：US20130196498A1

    公开(公告)日：2013-08-01

    申请号：US13753936

    申请日：2013-01-30

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Chih-Ming Kuo ,  Yie-Chuan Chiu ,  Lung-Hua Ho

    IPC: H01L21/768

    CPC classification number: H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11472 ,  H01L2224/11903 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2224/05552

    Abstract: A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer.

    Abstract translation: 碰撞过程包括提供硅衬底; 在硅衬底上形成含钛金属层，所述含钛金属层包括多个第一区域和多个第二区域; 在含钛金属层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层以形成多个第一开口槽; 在第一开口槽内形成多个铜凸块，所述铜凸块包括第一顶表面和第一环表面; 去除第一光致抗蚀剂层; 在含钛金属层上形成第二光致抗蚀剂层; 图案化所述第二光致抗蚀剂层以形成多个第二开口槽; 在空间，第一顶表面和第一环表面处形成多个凸块隔离层; 在凸块隔离层上形成多个连接层; 去除第二光致抗蚀剂层，去除第二区域以形成凸起下的冶金层。

    CHIP
    48.
    发明申请
    CHIP 有权

    公开(公告)号：US20250038143A1

    公开(公告)日：2025-01-30

    申请号：US18753556

    申请日：2024-06-25

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Chun-Chia Yeh

    IPC: H01L23/00 ,  H01L23/31

    Abstract: A chip provided to be flip bonded to a circuit board includes at least one bump and at least one supportive element which protrudes from an active surface of the chip and is located between the bump and a first side of the active surface. The supportive element is provided to support a lead on the circuit board to prevent the lead from contacting a metal burr protruding from the active surface or a metal cut surface exposed on a side wall of the chip. The supportive element can protect the chip and the lead from short circuit or electrical abnormality.

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