公开(公告)号：US09361024B1

公开(公告)日：2016-06-07

申请号：US14594178

申请日：2015-01-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu

IPC: G06F3/06

CPC classification number: G06F12/0246 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C8/12 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3495

Abstract: A memory cell programming method for a rewritable non-volatile memory module is provided. The method includes grouping physical erasing units of the rewritable non-volatile memory module at least into a first area and a second area, wherein a first programming parameter set is configured initially for writing a first kind of data into the physical erasing units of the first area and the upper physical programming units of the physical erasing units of the first area are not written with data. The method also includes adjusting the first set of programming parameters to obtain a second programming parameter set, and applying the second set of programming parameters to write a second kind of data into the physical erasing units of the second area, wherein the upper physical programming units of the physical erasing units of the second area are not written with data.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的存储单元编程方法。 该方法包括至少将可重写非易失性存储器模块的物理擦除单元分组到第一区域和第二区域中，其中第一编程参数组最初被配置为将第一种类型的数据写入到第一区域和第二区域的物理擦除单元 区域和第一区域的物理擦除单元的上层物理编程单元没有写入数据。 该方法还包括调整第一组编程参数以获得第二编程参数集，以及应用第二组编程参数将第二类数据写入第二区的物理擦除单元，其中上层物理编程单元 的第二区域的物理擦除单元没有写入数据。

公开(公告)号：US09257204B2

公开(公告)日：2016-02-09

申请号：US14018436

申请日：2013-09-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Siu-Tung Lam ,  Tzung-Lin Wu ,  Kuo-Yi Cheng

IPC: G11C29/00 ,  G11C29/50 ,  G11C16/26 ,  G11C29/02 ,  G11C16/34 ,  G11C16/00

CPC classification number: G11C29/50004 ,  G11C16/00 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028

Abstract: A read voltage setting method for a rewritable non-volatile memory module is provided. The method includes: reading test data stored in memory cells of a word line to obtain a corresponding critical voltage distribution and identifying a default read voltage corresponding to the word line based on the corresponding critical voltage distribution; applying a plurality of test read voltages obtained according to the default read voltage to the word line to read a plurality of test page data; and determining an optimized read voltage corresponding to the word line according to the minimum error bit number among a plurality of error bit numbers of the test page data. The method further includes calculating a difference value between the default read voltage and the optimized read voltage as a read voltage adjustment value corresponding to the word line and recording the read voltage adjustment value in a retry table.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的读取电压设置方法。 该方法包括：读取存储在字线的存储单元中的测试数据，以获得相应的临界电压分布，并基于相应的临界电压分布识别与字线对应的默认读取电压; 将根据所述默认读取电压获得的多个测试读取电压施加到所述字线以读取多个测试页面数据; 以及根据所述测试页数据的多个错误位数中的最小误差位数确定与所述字线对应的优化读取电压。 该方法还包括计算默认读取电压和优化读取电压之间的差值作为对应于字线的读取电压调整值，并将读取电压调整值记录在重试表中。

公开(公告)号：US20150095741A1

公开(公告)日：2015-04-02

申请号：US14109959

申请日：2013-12-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1048

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一读取电压读取存储器单元以获得第一验证位; 执行包括根据第一验证位的概率解码算法的解码过程以获得第一解码比特，并且通过使用解码比特来确定解码是否成功; 如果解码失败，则根据第二读取电压读取存储器单元以获得第二验证位，并且根据第二验证位执行解码过程以获得第二解码位。 第二读取电压与第一读取电压不同，第二读取电压的数量等于第一读取电压的数量。 因此，能够提高校正误差的能力。

公开(公告)号：US20140325118A1

公开(公告)日：2014-10-30

申请号：US13935572

申请日：2013-07-05

Applicant: Phison Electronics Corp.

Inventor： Kuo-Yi Cheng ,  Wei Lin ,  Kim-Hon Wong ,  Hao-Zhi Lee ,  Hung-Chun Lin ,  Chun-Yen Chang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G11C7/04 ,  G11C11/5628 ,  G11C29/82

Abstract: A data writing method for writing data into a physical erasing unit and a memory controller and a memory storage apparatus using the data writing method are provided. The method includes dividing the data into a plurality of information frames in a unit of one physical programming unit. The method also includes writing the information frames in sequence into at least one physical programming unit constituted by memory cells disposed on at least one first word line and programming the storage state of memory cells disposed on at least one second word line following the first word line to an auxiliary pattern. Accordingly, the method effectively prevents data stored in the physical erasing unit, which is not full of data, from being lost due to a high temperature.

Abstract translation: 提供了一种用于将数据写入物理擦除单元和存储器控制器以及使用数据写入方法的存储器装置的数据写入方法。 该方法包括以一个物理编程单元为单位将数据划分成多个信息帧。 该方法还包括将信息帧顺序地写入至少一个物理编程单元，该物理编程单元由设置在至少一个第一字线上的存储单元构成，并且对位于第一字线之后的至少一个第二字线上的存储单元的存储状态进行编程 到辅助模式。 因此，该方法有效地防止存储在不充满数据的物理擦除单元中的数据由于高温而丢失。

公开(公告)号：US12293792B2

公开(公告)日：2025-05-06

申请号：US18298335

申请日：2023-04-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Cheng Su ,  Po-Hao Chen ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G11C16/08 ,  G11C16/26 ,  G11C16/34

Abstract: A voltage prediction method, a memory storage device and a memory control circuit unit are disclosed. The method includes: reading a plurality of memory cells in a rewritable non-volatile memory module by using a first read voltage level to obtain count information, and the first read voltage level is configured to distinguish a first state and a second state adjacent to each other in a threshold voltage distribution of the memory cells, and the count information reflects a total number of first memory cells meeting a target condition among the memory cells; and predicting a second read voltage level according to the count information, and the second read voltage level is configured to distinguish a third state and a fourth state adjacent to each other in the threshold voltage distribution.

公开(公告)号：US20250060872A1

公开(公告)日：2025-02-20

申请号：US18461534

申请日：2023-09-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Jian Ping Syu ,  Szu-Wei Chen ,  An-Cin Li

IPC: G06F3/06

Abstract: A data storage method, a host system, and a data storage system are disclosed. The method includes the following. An artificial intelligence (AI) model is executed. First data to be stored to a memory storage device is obtained. In response to the first data being generated by the AI model, second data is generated according to the first data, in which the second data includes the first data, and a data amount of the second data is greater than a data amount of the first data. A first write command is sent to the memory storage device according to the second data, so as to instruct the memory storage device to store the second data.

公开(公告)号：US12197737B2

公开(公告)日：2025-01-14

申请号：US18168573

申请日：2023-02-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Cheng Su ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G06F3/06

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending at least one read command sequence instructing to read a first physical unit in a rewritable non-volatile memory module; receiving response data from the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first memory cell according to the plurality of identification bits; and decoding data read from the first memory cell according to the decoding parameter.

公开(公告)号：US11726709B2

公开(公告)日：2023-08-15

申请号：US16994668

申请日：2020-08-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Yu-Siang Yang ,  Szu-Wei Chen ,  Wei Lin

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/0483

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.

公开(公告)号：US20230195361A1

公开(公告)日：2023-06-22

申请号：US17577012

申请日：2022-01-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Po-Cheng Su ,  Chih-Wei Wang ,  Wei Lin

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.

公开(公告)号：US20220365706A1

公开(公告)日：2022-11-17

申请号：US17336347

申请日：2021-06-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Wei Lin ,  Shih-Jia Zeng ,  An-Cheng Liu ,  Yu-Cheng Hsu

IPC: G06F3/06

Abstract: A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.