公开(公告)号：US20160332867A1

公开(公告)日：2016-11-17

申请号：US14713287

申请日：2015-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lee-Chuan Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0041 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00293 ,  B81C2201/0112 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/0785

Abstract: An integrated circuit (IC) device is provided. The IC device includes a first substrate having a frontside and a backside. The backside includes a first cavity extending into the first substrate. A dielectric layer is disposed on the backside of the first substrate, and includes an opening corresponding to the first cavity and a trench extending laterally away from the opening and terminating at a gas inlet recess. A recess in the frontside of the first substrate extends downwardly from the frontside to the dielectric layer. The recess has substantially vertical upper sidewalls which adjoin lower sidewalls which taper inwardly from the substantially vertical sidewalls to points on the dielectric layer which circumscribe the gas inlet recess. A conformal sealant layer is arranged over the frontside of the first substrate, along the substantially vertical upper sidewalls, and along the lower sidewalls. The sealant layer hermetically seals the gas inlet recess.

Abstract translation: 提供集成电路（IC）装置。 IC器件包括具有前侧和后侧的第一基板。 背面包括延伸到第一基底中的第一腔。 电介质层设置在第一基板的背面，并且包括对应于第一空腔的开口和从开口横向延伸并终止于气体入口凹部的沟槽。 第一衬底的前侧的凹部从前侧向下延伸到电介质层。 凹部具有基本上垂直的上侧壁，其邻接下部侧壁，所述下侧壁从基本上垂直的侧壁向内逐渐向包围气体入口凹部的电介质层上的点倾斜。 共形密封剂层沿着基本垂直的上侧壁以及沿着下侧壁设置在第一基板的前侧上。 密封剂层密封气体入口凹部。

公开(公告)号：US09390936B2

公开(公告)日：2016-07-12

申请号：US14527039

申请日：2014-10-29

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY ,  Stephanie Tombrello

Inventor： Michael D. Henry ,  Andrew P. Homyk ,  Axel Scherer ,  Thomas A. Tombrello ,  Sameer Walavalkar

IPC: G01N1/18 ,  H01L21/308 ,  B81C1/00 ,  H01L21/3065 ,  G01N1/40

CPC classification number: B81C1/00111 ,  B01J19/0046 ,  B01J2219/00504 ,  B01J2219/00664 ,  B81B1/006 ,  B81B2203/0361 ,  B81B2207/056 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0159 ,  G01N1/405 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3086 ,  Y10T436/25375

Abstract: Methods for fabricating of high aspect ratio probes and deforming micropillars and nanopillars are described. Use of polymers in deforming nanopillars and micropillars is also described.

公开(公告)号：US09096420B2

公开(公告)日：2015-08-04

申请号：US13790617

申请日：2013-03-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

IPC: H01L27/14 ,  B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0059 ,  B81B3/0056 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81C1/00158 ,  B81C1/00714 ,  B81C2201/0112 ,  B81C2201/0132 ,  G01C19/5719 ,  G01P15/0802 ,  G01P15/125

Abstract: Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed.

Abstract translation: 用于形成MEMS器件的方法和装置。 一种装置包括具有第一厚度的半导体衬底的至少一部分并被图案化以形成可移动质量块; 形成第一电容的第一板的移动感测电极; 所述至少一个锚定体从所述半导体衬底图案化并且具有形成所述第一电容的所述第二板的部分并与所述第一板间隔开第一间隙; 图案化的第二厚度的半导体材料层，以形成形成第二电容的第一板的第一电极，并进一步图案化以形成覆盖至少一个锚的第二电极，并形成间隔第二间隙的第二板，该第二间隔较小 比第一个差距; 其中形成的总电容是第一电容和第二电容之和。 公开了方法。

公开(公告)号：US20150021745A1

公开(公告)日：2015-01-22

申请号：US14336477

申请日：2014-07-21

Applicant: Atlantic lnertial Systems Limited

Inventor： Tracey Hawke ,  Mark Venables ,  lan Sturland ,  Rebecka Eley

IPC: B81C1/00 ,  B81B3/00 ,  H01L21/3065 ,  H01L21/308

CPC classification number: B81C1/00531 ,  B81B3/0064 ,  B81B2201/033 ,  B81B2203/033 ,  B81C1/00388 ,  B81C1/00619 ,  B81C2201/0112 ,  H01L21/3065 ,  H01L21/308

Abstract: A method of reactive ion etching a substrate 46 to form at least a first and a second etched feature (42, 44) is disclosed. The first etched feature (42) has a greater aspect ratio (depth:width) than the second etched feature (44). In a first etching stage the substrate (46) is etched so as to etch only said first feature (42) to a predetermined depth. Thereafter in a second etching stage, the substrate (46) is etched so as to etch both said first and said second features (42, 44) to a respective depth. A mask (40) may be applied to define apertures corresponding in shape to the features (42, 44). The region of the substrate (46) in which the second etched feature (44) is to be produced is selectively masked with a second maskant (50) during the first etching stage, The second maskant (50) is then removed prior to the second etching stage.

Abstract translation: 公开了一种反应离子蚀刻衬底46以形成至少第一和第二蚀刻特征（42,44）的方法。 第一蚀刻特征（42）具有比第二蚀刻特征（44）更大的纵横比（深度：宽度）。 在第一蚀刻阶段中，蚀刻衬底（46）以仅将所述第一特征（42）仅蚀刻到预定深度。 此后，在第二蚀刻阶段，蚀刻衬底（46）以便将所述第一和第二特征（42,44）都蚀刻到相应的深度。 可以施加掩模（40）以限定形状对应于特征（42,44）的孔。 在第一蚀刻阶段期间，用第二掩模（50）选择性地掩蔽其中要产生第二蚀刻特征（44）的衬底（46）的区域，然后在第二蚀刻阶段之前将第二掩模（50） 蚀刻阶段。

公开(公告)号：US08871105B2

公开(公告)日：2014-10-28

申请号：US13416465

申请日：2012-03-09

Applicant: Jaroslaw W. Winniczek ,  Frank Y. Lin ,  Alan J. Miller ,  Qing Xu ,  Seongjun Heo ,  Jin Hwan Ham ,  Sang Joon Yoon ,  Camelia Rusu

Inventor： Jaroslaw W. Winniczek ,  Frank Y. Lin ,  Alan J. Miller ,  Qing Xu ,  Seongjun Heo ,  Jin Hwan Ham ,  Sang Joon Yoon ,  Camelia Rusu

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/30655 ,  B81C1/00619 ,  B81C2201/0112 ,  H01L21/3086

Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.

Abstract translation: 提供了一种用于在等离子体处理室中蚀刻硅的方法，其具有工作压力和工作偏压。 该方法包括：在硅中执行第一垂直蚀刻以产生具有第一深度和侧壁的孔; 在侧壁上进行保护层的沉积; 执行第二垂直蚀刻以将所述孔加深到第二深度并且产生第二侧壁，所述第二侧壁包括第一槽，第二槽和峰，所述第一槽对应于所述第一侧壁，所述第二槽对应于 第二侧壁，该峰设置在第一槽和第二槽之间; 并进行第三次蚀刻以降低峰值。

公开(公告)号：US08796791B2

公开(公告)日：2014-08-05

申请号：US13888920

申请日：2013-05-07

Applicant: Axel Franke ,  Patrick Wellner ,  Lars Tebje

Inventor： Axel Franke ,  Patrick Wellner ,  Lars Tebje

IPC: G01P15/08

CPC classification number: B81B3/0075 ,  B81C1/00626 ,  B81C1/00674 ,  B81C2201/0112 ,  B81C2201/014 ,  B81C2203/0109

Abstract: Measures are proposed by which the design freedom is significantly increased in the case of the implementation of the micromechanical structure of the MEMS element of a component, which includes a carrier for the MEMS element and a cap for the micromechanical structure of the MEMS element, the MEMS element being mounted on the carrier via a standoff structure. The MEMS element is implemented in a layered structure, and the micromechanical structure of the MEMS element extends over at least two functional layers of this layered structure, which are separated from one another by at least one intermediate layer.

Abstract translation: 提出的措施是，在实现元件的MEMS元件的微机械结构的情况下，设计自由度显着增加，其包括用于MEMS元件的载体和用于MEMS元件的微机械结构的盖， MEMS元件通过支架结构安装在载体上。 MEMS元件以分层结构实现，并且MEMS元件的微机械结构在该分层结构的至少两个功能层上延伸，所述功能层通过至少一个中间层彼此分离。

公开(公告)号：US08633116B2

公开(公告)日：2014-01-21

申请号：US13387670

申请日：2011-01-25

Applicant: Manabu Yoshii ,  Kazuhiro Watanabe

Inventor： Manabu Yoshii ,  Kazuhiro Watanabe

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/30655 ,  B81C1/00087 ,  B81C2201/0112 ,  H01L21/3065

Abstract: A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step.

Abstract translation: 干蚀刻方法包括第一步骤和第二步骤。 第一步骤包括从包括氧化气体和含氟气体的气体混合物产生第一等离子体，并且在硅层上用第一等离子体进行各向异性蚀刻，以在硅层中形成凹陷。 第二步骤包括交替地重复有机膜形成过程，其中有机膜用第二等离子体沉积在凹陷的内表面上，并且蚀刻工艺使得被有机膜覆盖的凹槽用第一等离子体各向异性蚀刻。 当蚀刻停止层从第一步骤形成的凹部的底面的一部分露出时，第一步骤切换到第二步骤。

公开(公告)号：US20130237062A1

公开(公告)日：2013-09-12

申请号：US13416465

申请日：2012-03-09

Applicant: Jaroslaw W. Winniczek ,  Frank Y. Lin ,  Alan J. Miller ,  Qing Xu ,  Seongjun Heo ,  Jin Hwan Ham ,  Sang Joon Yoon ,  Camelia Rusu

Inventor： Jaroslaw W. Winniczek ,  Frank Y. Lin ,  Alan J. Miller ,  Qing Xu ,  Seongjun Heo ,  Jin Hwan Ham ,  Sang Joon Yoon ,  Camelia Rusu

IPC: H01L21/3065

CPC classification number: H01L21/30655 ,  B81C1/00619 ,  B81C2201/0112 ,  H01L21/3086

Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.

Abstract translation: 提供了一种用于在等离子体处理室中蚀刻硅的方法，其具有工作压力和工作偏压。 该方法包括：在硅中执行第一垂直蚀刻以产生具有第一深度和侧壁的孔; 在侧壁上进行保护层的沉积; 执行第二垂直蚀刻以将所述孔加深到第二深度并产生第二侧壁，所述第二侧壁包括第一槽，第二槽和峰，所述第一槽对应于所述第一侧壁，所述第二槽对应于 第二侧壁，该峰设置在第一槽和第二槽之间; 并进行第三次蚀刻以降低峰值。

公开(公告)号：US08354033B2

公开(公告)日：2013-01-15

申请号：US12227509

申请日：2007-04-27

Applicant: Dick Scholten ,  Julia Cassemeyer ,  Michael Stumber ,  Franz Laermer ,  Ando Feyh ,  Christian Maeurer

Inventor： Dick Scholten ,  Julia Cassemeyer ,  Michael Stumber ,  Franz Laermer ,  Ando Feyh ,  Christian Maeurer

IPC: B44C1/22 ,  C25F3/00

CPC classification number: B81C1/00119 ,  A61M37/0015 ,  A61M2037/003 ,  A61M2037/0038 ,  A61M2037/0046 ,  A61M2037/0053 ,  B81C2201/0112 ,  B81C2201/0115

Abstract: A method for producing porous microneedles (10) situated in an array on a silicon substrate includes: providing a silicon substrate, applying a first etching mask, patterning microneedles using a DRIE process (“deep reactive ion etching”), removing the first etching mask, at least partially porosifying the Si substrate, the porosification beginning on the front side of the Si substrate and a porous reservoir being formed.

Abstract translation: 一种制造位于硅衬底上的多孔微针（10）的方法，包括：提供硅衬底，施加第一蚀刻掩模，使用DRIE工艺（深反应离子蚀刻）图案化微针，去除第一蚀刻掩模， 至少部分地使Si衬底开孔，从Si衬底的正面开始的开孔化和形成的多孔容器。

公开(公告)号：US20120152895A1

公开(公告)日：2012-06-21

申请号：US13305992

申请日：2011-11-29

Applicant: ROBERT P. CHEBI ,  ALAN CHESHIRE ,  GABRIEL ROUPILLARD ,  ALFREDO GRANADOS

Inventor： ROBERT P. CHEBI ,  ALAN CHESHIRE ,  GABRIEL ROUPILLARD ,  ALFREDO GRANADOS

IPC: C23F1/00

CPC classification number: H01L21/30655 ,  B81B2203/033 ,  B81C1/00619 ,  B81C2201/0112 ,  H01J37/32403 ,  H01L21/67069 ,  H01L21/67748 ,  H01L21/6831

Abstract: Methods for etching a substrate in a plasma etch reactor may include (a) depositing polymer on surfaces of a feature formed in substrate disposed in the etch reactor using first reactive species formed from a first process gas comprising a polymer forming gas; (b) etching the bottom surface of the feature of the substrate in the etch reactor using a third reactive species formed from a third process gas including an etching gas; and (c) bombarding a bottom surface of the feature with a second reactive species formed from a second process gas comprising one or more of an inert gas, an oxidizing gas, a reducing gas, or the polymer forming gas while at least one of depositing the polymer to remove at least some of the polymer disposed on the bottom surface or etching the bottom surface to at least one of chemically or physically damage the bottom surface.

Abstract translation: 用于蚀刻等离子体蚀刻反应器中的衬底的方法可以包括（a）使用由包含聚合物形成气体的第一工艺气体形成的第一反应性物质将形成在衬底中的特征的表面上沉积聚合物; （b）使用由包括蚀刻气体的第三工艺气体形成的第三反应性物质蚀刻所述蚀刻反应器中所述衬底的所述特征的底表面; 和（c）用包含一种或多种惰性气体，氧化气体，还原性气体或形成聚合物的气体的第二工艺气体形成的第二反应性物质轰击所述特征的底部表面，同时沉积 所述聚合物除去布置在底表面上的至少一些聚合物或蚀刻底表面至少一种化学或物理损伤底表面。