公开(公告)号：US08345433B2

公开(公告)日：2013-01-01

申请号：US11177508

申请日：2005-07-08

Applicant: George E. White ,  Sidharth Dalmia ,  Venkatesh Sundaram ,  Madhavan Swaminathan

Inventor： George E. White ,  Sidharth Dalmia ,  Venkatesh Sundaram ,  Madhavan Swaminathan

IPC: H05K1/18

CPC classification number: H05K1/186 ,  H01L21/4857 ,  H01L23/055 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/183 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/061 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Organic laminate stack ups are disclosed for a variety of applications, including high frequency RF applications. One or more inner core layers may be disposed between outer layers along with bondply or prepreg layers as needed. Discrete devices, including surface mount components and flip chips, may be embedded within the organic laminate stack up structures. The embedding of the discrete devices, which may be active or passive devices, may be in the form of a layer of bondply or prepreg encapsulating the discrete devices. In addition or in the alternative, cavities may be formed in at least the outer layers for housing discrete devices, which include surface mount components, flip chips, and wire bonded integrated circuits. A variety of caps may be utilized to seal the cavities. Further, shielding may be provided for the organic laminate stack up structure, including through a wall of vias or a plated trench cut along at least one side of the stack up structure. Each stack up structure may be packaged in a variety of ways, including as a surface mount component, ball grid array, or land grid array.

Abstract translation: 公开了有机层压叠层用于各种应用，包括高频RF应用。 根据需要，一个或多个内芯层可以与键合层或预浸料层一起设置在外层之间。 分立器件，包括表面贴装元件和倒装芯片，可嵌入有机叠层堆叠结构内。 可以是有源或无源器件的分立器件的嵌入可以是封装分立器件的键合层或预浸料的形式。 另外或在替代方案中，空腔可以形成在至少外层中，用于容纳包括表面安装部件，倒装芯片和引线键合集成电路的分立器件。 可以使用各种盖来密封空腔。 此外，可以提供用于有机层叠叠层结构的屏蔽，包括穿过通孔壁或沿堆叠结构的至少一侧切割的电镀沟槽。 每个堆叠结构可以以各种方式包装，包括作为表面安装部件，球栅阵列或平台网格阵列。

公开(公告)号：US08336205B2

公开(公告)日：2012-12-25

申请号：US13209052

申请日：2011-08-12

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: H01K3/10

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83132 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K1/036 ,  H05K1/188 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层，第二绝缘层和导电膜的基底基板的方法制造印刷线路板。 在基于对准标记确定的位置处将电子部件放置在第一绝缘层上。 在将电子部件封闭在第二绝缘层的开口内之后，在基于对准标记确定的位置处形成暴露电子部件的端子的通孔，该位置用于确定电子部件的位置。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。

公开(公告)号：US08324512B2

公开(公告)日：2012-12-04

申请号：US13004325

申请日：2011-01-11

Applicant: Yukihiko Toyoda ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

Inventor： Yukihiko Toyoda ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/116 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09745 ,  H01L2924/00

Abstract: A multilayered printed circuit board including a substrate, a multilayered structure built thereon and having conductor circuits and interlaminar resin insulating layers in an alternate fashion, and one or more stack-via structures including via-holes stacked one another and electrically connected to the conductor circuits through the insulating layers. Each of the via-holes includes a land portion formed on a respective one of the insulating layers and a filled via structure portion filling an opening of the respective one of the insulating layers with a metal layer such that the via-holes are stacked one another immediately above the filled via structure portion of each via-hole, the via-holes include the outermost layer via-hole in the outermost layer of the insulating layers, and one or more via-holes have the land portion having the land diameter which is larger than the land diameter of the land portion of the outermost layer via-hole.

Abstract translation: 一种多层印刷电路板，包括基板，在其上构建的多层结构，并且具有交替形式的导体电路和层间树脂绝缘层，以及一个或多个堆叠通孔结构，其包括彼此堆叠并且电连接到导体电路的通孔 通过绝缘层。 每个通孔包括形成在绝缘层的相应一个上的接合部分和填充的通孔结构部分，其中填充有绝缘层的相应一个绝缘层的开口的金属层使得通孔彼此堆叠 在通孔的填充通孔结构部分的正上方，通孔包括绝缘层的最外层中的最外层通孔，一个或多个通孔具有焊盘直径为 大于最外层通孔的陆部的陆部直径。

公开(公告)号：US20120273116A1

公开(公告)日：2012-11-01

申请号：US13536815

申请日：2012-06-28

Applicant: Young Ho SOHN ,  Seog Moon CHOI ,  Sung Keun PARK ,  Young Ki LEE ,  Bum Sik JANG ,  Ji Hyun PARK

Inventor： Young Ho SOHN ,  Seog Moon CHOI ,  Sung Keun PARK ,  Young Ki LEE ,  Bum Sik JANG ,  Ji Hyun PARK

IPC: B32B38/04 ,  B32B38/08

CPC classification number: H05K3/4623 ,  H05K1/056 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096

Abstract: Disclosed herein is a heat dissipating substrate having a structure in which two two-layered core substrates, each including a metal core functioning to radiate heat, are laminated and connected in parallel to each other, thus accomplishing more improved radiation performance, and a method of manufacturing the same.

Abstract translation: 本发明公开了一种散热基板，其结构是将两个分别包含发热功能的金属芯片的两层芯基板彼此并联并相互并联，从而实现更好的辐射性能， 制造相同。

公开(公告)号：US08288663B2

公开(公告)日：2012-10-16

申请号：US12345364

申请日：2008-12-29

Applicant: Tsung-Yuan Chen ,  Shu-Sheng Chiang ,  David C. H. Cheng

Inventor： Tsung-Yuan Chen ,  Shu-Sheng Chiang ,  David C. H. Cheng

IPC: H01K1/11

CPC classification number: H05K3/465 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/0038 ,  H05K3/107 ,  H05K3/426 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09736 ,  Y10T29/49147

Abstract: An electrical interconnecting structure suitable for a circuit board is provided. The electrical interconnecting structure includes a core, an ultra fine pattern, and a patterned conductive layer. The core has a surface, and the ultra fine pattern is inlaid in the surface of the core. The patterned conductive layer is disposed on the surface of the core and is partially connected to the ultra fine pattern. Since the ultra fine pattern of the electrical interconnecting structure is inlaid in the surface of the core and is partially connected to the patterned conductive layer located on the surface of the core.

Abstract translation: 提供了适用于电路板的电互连结构。 电互连结构包括芯，超细图案和图案化导电层。 芯具有表面，并且超细图案镶嵌在芯的表面中。 图案化导电层设置在芯的表面上并且部分地连接到超细图案。 由于电互连结构的超细图案镶嵌在芯的表面中，并且部分地连接到位于芯的表面上的图案化导电层。

公开(公告)号：US08256106B2

公开(公告)日：2012-09-04

申请号：US12010345

申请日：2008-01-24

Applicant: Chung-Cheng Lien ,  Chih-Kui Yang

Inventor： Chung-Cheng Lien ,  Chih-Kui Yang

IPC: H05K1/16 ,  H05K3/02 ,  H05K3/32 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance.

Abstract translation: 公开了一种其中嵌有电容器的电路板结构及其制造方法。 该结构包括至少两个核心层，其单独地包括具有两个相对表面的电介质层，设置在电介质层的两个相对表面的外侧的电路层，以及分别嵌入在介电层的两个相对表面的内部的内部的至少两个电容器 所述电介质层与所述电路层在同一侧分别电连接; 设置在所述芯层之间的至少一个粘合剂层，以将所述芯层组合为芯结构; 以及穿透芯层和粘合剂层的至少一个导电通孔，并且电连接芯层的电路层。 因此，本发明可以提高电路布局的灵活性，并且实现电容器之间的并联以提供更多的电容。

公开(公告)号：US08250751B2

公开(公告)日：2012-08-28

申请号：US12070811

申请日：2008-02-20

Applicant: Rajwant Sidhu ,  Paul Walker

Inventor： Rajwant Sidhu ,  Paul Walker

IPC: H01K3/10

CPC classification number: H05K1/115 ,  H05K1/0201 ,  H05K3/423 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2203/1476 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Printed circuit boards have circuit layers with one or more copper filled through-holes and methods of manufacturing the same. An aspect of an embodiment of the present invention enhances thermal characteristics of filled through-holes of printed circuit boards to provide extra reliability to the printed circuit boards. In one embodiment, a printed circuit broad has a plurality of through-holes to connect copper patterns on different layers of the printed circuits broad. Here, at least one of the through-holes is copper plated closed at both ends with at least 70% volume of the through-hole plated with copper to, e.g., enhance thermal characteristics of the through-hole, thereby providing extra reliability to the printed circuit board. In one embodiment, the printed circuit board includes a surface conductor (or cap) that is directly plated over the copper filled barrel plated through-hole.

Abstract translation: 印刷电路板具有带有一个或多个铜填充通孔的电路层及其制造方法。 本发明的实施例的一个方面提高了印刷电路板的填充通孔的热特性，从而为印刷电路板提供了额外的可靠性。 在一个实施例中，印刷电路布线具有多个通孔，以连接印刷电路的不同层上的铜图案。 这里，至少一个通孔在两端被镀铜封闭，至少70％体积的通孔镀有铜，例如增强了通孔的热特性，从而为 印刷电路板。 在一个实施例中，印刷电路板包括直接电镀在铜填充的圆柱形电镀通孔上的表面导体（或帽）。

公开(公告)号：US08238700B2

公开(公告)日：2012-08-07

申请号：US12757418

申请日：2010-04-09

Applicant: Motoo Asai ,  Hiroaki Kodama ,  Kazuhito Yamada

Inventor： Motoo Asai ,  Hiroaki Kodama ,  Kazuhito Yamada

IPC: G02B6/12 ,  G02B6/10

CPC classification number: G02B6/43 ,  G02B6/4214 ,  H05K1/0274 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/09536

Abstract: A multilayer printed circuit board including insulating layers, conductor circuits formed between the insulating layers, and optical circuits formed between the insulating layers and including a first optical circuit. The first optical circuit is positioned on a first outermost insulating layer of the insulating layers, and the insulating layers, conductor circuits and optical circuits are layered to form a multilayer structure having a first surface and a second surface on an opposite side of the first surface such that the multilayer structure is structured to mount optical elements on the first surface and second surface of the multilayer structure, respectively.

Abstract translation: 一种多层印刷电路板，包括绝缘层，形成在绝缘层之间的导体电路以及形成在绝缘层之间并包括第一光学电路的光电路。 第一光电路位于绝缘层的第一绝缘绝缘层上，绝缘层，导体电路和光电路被层叠形成具有第一表面和第二表面的第一表面的第二表面的多层结构 使得多层结构被分别安装在多层结构的第一表面和第二表面上的光学元件。

公开(公告)号：US08232477B2

公开(公告)日：2012-07-31

申请号：US12494798

申请日：2009-06-30

Applicant: Kazunori Kitamura ,  Yukihiro Koga ,  Kiyoshi Sato

Inventor： Kazunori Kitamura ,  Yukihiro Koga ,  Kiyoshi Sato

IPC: H05K1/03 ,  H01L23/053 ,  H01L23/12

CPC classification number: H05K3/0094 ,  C08K3/013 ,  C08K2201/003 ,  C08L63/00 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T428/24917

Abstract: In a curable resin composition containing an inorganic filler, the average particle diameter of the inorganic filler is 1 μm or less and the content of the inorganic filler is 50 wt % or less. The curable resin composition can be preferably used for a halogen-free resin substrate and the like having a small load on an environment as a hole-plugging curable resin composition as well as used to provide a hole-plugging build-up printed wiring board having a via-on-via structure (in particular, a stacked via structure) having an excellent crack-resistant property, an excellent insulation/connection reliability, and the like.

Abstract translation: 在含有无机填料的固化性树脂组合物中，无机填料的平均粒径为1μm以下，无机填料的含量为50重量％以下。 固化性树脂组合物可以优选用于作为空穴堵塞固化性树脂组合物的环境负荷小的无卤素树脂基材等，并且用于提供具有孔堵塞积聚印刷线路板，其具有 具有优异的抗裂性，优异的绝缘/连接可靠性等的通孔通孔结构（特别是堆叠通孔结构）。

公开(公告)号：US08203395B2

公开(公告)日：2012-06-19

申请号：US12542447

申请日：2009-08-17

Applicant: Fei Guo ,  Xiao Ling Shi ,  Mark Frankovitch ,  Wasim Ullah

Inventor： Fei Guo ,  Xiao Ling Shi ,  Mark Frankovitch ,  Wasim Ullah

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09709 ,  H05K2201/09727 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Various apparatus and methods of addressing crosstalk in a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first layer of a circuit board with a first signal trace and forming a second layer of the circuit board with a second signal trace. A first guard trace is formed on the first layer and offset laterally from the first signal trace but at least partially overlapping the second signal trace and a second guard trace is formed on the second layer and offset laterally from the second signal trace but at least partially overlapping the first signal trace.

Abstract translation: 公开了解决电路板中的串扰的各种装置和方法。 一方面，提供了一种制造方法，其包括用第一信号迹线形成电路板的第一层，并用第二信号迹线形成电路板的第二层。 第一保护迹线形成在第一层上并且从第一信号迹线侧向偏移，但是至少部分地与第二信号迹线重叠，并且第二保护迹线形成在第二层上并且从第二信号迹线侧向偏移，但是至少部分地 重叠第一个信号迹线。